Design & Implementation of Programmable CRC Computation using FPGA: CRC as a modem error-correcting Code - Couverture souple

Murade, Rameshwar; Ingale, Pavan; Kale, Rahul

 
9783659162602: Design & Implementation of Programmable CRC Computation using FPGA: CRC as a modem error-correcting Code
Couverture souple
ISBN 10 : 3659162604 ISBN 13 : 9783659162602
Editeur : LAP LAMBERT Academic Publishing, 2014

Synopsis

Good error control performance requires the scheme to be selected based on the characteristics of the communication channel. Consequently, error-detecting and correcting codes can be generally distinguished between random-error-detecting/correcting and burst-error-detecting/correcting. Cyclic codes have favorable properties in that they are well suited for detecting burst errors. The cyclic redundancy check (CRC) is an error detection technique that is widely utilized in digital data communication and other fields such as data storage, data compression, etc. The work presented in describes the FPGA implementation of a CRC Decoder that has the advantages of correcting more than one bit error. Since we are introducing the hardware implementation of CRC with error correction, our main concern is about the design of the CRC decoder with error correcting capabilities. Such an optimized circuit represents an attractive hard macro for environments requiring low cost hardware flexibility, and in emerging areas such as ISCSI-based SANs, where the flexibility to adopt emerging protocols offers a key advantage to vendors.

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Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2014
Langue
anglais
ISBN 10 
3659162604
ISBN 13 
9783659162602
Reliure
Broché
Nombre de pages
104
Coordonnées du fabricant
non disponible
Personne responsable
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