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Response Data Compression Techniques in Digital Circuit Testing: Study and Evaluation - Couverture souple
Synopsis
Today, digital logic circuits are essential embedded parts of devices that are critically important due to impact on public safety. Such devices include transportation, human implants and critical systems’ management where Fault-Tolerant (FT) concept is the bottom line. To implement the concept of FT it is essential to test the system accurately to measure all the critical parameters of a dependable system. Challenges of testing has become more difficult due to ubiquitous and complexity of digital systems. Exhaustive testing is impossible and ATEs are not commonly affordable that led to the design concepts of DFT and BIST techniques. Due to the problems of storing huge response data the data compression techniques (RDC) like One's Count, Transition Count, Syndrome Testing, Walsh Spectra Coefficients, Signature Analysis, etc. are used in practicing testing. However, the problems of Aliasing are inevitable in RDC techniques. Embodied in this book is the study and evaluations of the effectiveness of various RDC techniques while applied individually. The results of extended study and evaluations of combinations of different RDC techniques are also part of the contents of the book.
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Présentation de l'éditeur
Today, digital logic circuits are essential embedded parts of devices that are critically important due to impact on public safety. Such devices include transportation, human implants and critical systems’ management where Fault-Tolerant (FT) concept is the bottom line. To implement the concept of FT it is essential to test the system accurately to measure all the critical parameters of a dependable system. Challenges of testing has become more difficult due to ubiquitous and complexity of digital systems. Exhaustive testing is impossible and ATEs are not commonly affordable that led to the design concepts of DFT and BIST techniques. Due to the problems of storing huge response data the data compression techniques (RDC) like One's Count, Transition Count, Syndrome Testing, Walsh Spectra Coefficients, Signature Analysis, etc. are used in practicing testing. However, the problems of Aliasing are inevitable in RDC techniques. Embodied in this book is the study and evaluations of the effectiveness of various RDC techniques while applied individually. The results of extended study and evaluations of combinations of different RDC techniques are also part of the contents of the book.
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Response Data Compression Techniques in Digital Circuit Testing
Edité par
LAP LAMBERT Academic Publishing, 2014
ISBN 10 : 3659239615
ISBN 13 : 9783659239618
Neuf
Couverture souple
Vendeur : moluna, Greven, Allemagne
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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Al-Balushi JaberJ. AlBalushi holds ME, BEA. Ahmad is currently with Sultan Qaboos University in Oman, holds PhD, MScEng, BScEng degrees and a PG diploma. With over 36 years of professional experience with universities and industrie. N° de réf. du vendeur 5142220
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Response Data Compression Techniques in Digital Circuit Testing
Edité par
LAP LAMBERT Academic Publishing Nov 2014, 2014
ISBN 10 : 3659239615
ISBN 13 : 9783659239618
Neuf
Taschenbuch
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Today, digital logic circuits are essential embedded parts of devices that are critically important due to impact on public safety. Such devices include transportation, human implants and critical systems' management where Fault-Tolerant (FT) concept is the bottom line. To implement the concept of FT it is essential to test the system accurately to measure all the critical parameters of a dependable system. Challenges of testing has become more difficult due to ubiquitous and complexity of digital systems. Exhaustive testing is impossible and ATEs are not commonly affordable that led to the design concepts of DFT and BIST techniques. Due to the problems of storing huge response data the data compression techniques (RDC) like One's Count, Transition Count, Syndrome Testing, Walsh Spectra Coefficients, Signature Analysis, etc. are used in practicing testing. However, the problems of Aliasing are inevitable in RDC techniques. Embodied in this book is the study and evaluations of the effectiveness of various RDC techniques while applied individually. The results of extended study and evaluations of combinations of different RDC techniques are also part of the contents of the book. 96 pp. Englisch. N° de réf. du vendeur 9783659239618
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Response Data Compression Techniques in Digital Circuit Testing : Study and Evaluation
Edité par
LAP LAMBERT Academic Publishing, 2014
ISBN 10 : 3659239615
ISBN 13 : 9783659239618
Neuf
Taschenbuch
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Today, digital logic circuits are essential embedded parts of devices that are critically important due to impact on public safety. Such devices include transportation, human implants and critical systems' management where Fault-Tolerant (FT) concept is the bottom line. To implement the concept of FT it is essential to test the system accurately to measure all the critical parameters of a dependable system. Challenges of testing has become more difficult due to ubiquitous and complexity of digital systems. Exhaustive testing is impossible and ATEs are not commonly affordable that led to the design concepts of DFT and BIST techniques. Due to the problems of storing huge response data the data compression techniques (RDC) like One's Count, Transition Count, Syndrome Testing, Walsh Spectra Coefficients, Signature Analysis, etc. are used in practicing testing. However, the problems of Aliasing are inevitable in RDC techniques. Embodied in this book is the study and evaluations of the effectiveness of various RDC techniques while applied individually. The results of extended study and evaluations of combinations of different RDC techniques are also part of the contents of the book. N° de réf. du vendeur 9783659239618
Quantité disponible : 1 disponible(s)
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Response Data Compression Techniques in Digital Circuit Testing
Edité par
LAP LAMBERT Academic Publishing Nov 2014, 2014
ISBN 10 : 3659239615
ISBN 13 : 9783659239618
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Today, digital logic circuits are essential embedded parts of devices that are critically important due to impact on public safety. Such devices include transportation, human implants and critical systems¿ management where Fault-Tolerant (FT) concept is the bottom line. To implement the concept of FT it is essential to test the system accurately to measure all the critical parameters of a dependable system. Challenges of testing has become more difficult due to ubiquitous and complexity of digital systems. Exhaustive testing is impossible and ATEs are not commonly affordable that led to the design concepts of DFT and BIST techniques. Due to the problems of storing huge response data the data compression techniques (RDC) like One's Count, Transition Count, Syndrome Testing, Walsh Spectra Coefficients, Signature Analysis, etc. are used in practicing testing. However, the problems of Aliasing are inevitable in RDC techniques. Embodied in this book is the study and evaluations of the effectiveness of various RDC techniques while applied individually. The results of extended study and evaluations of combinations of different RDC techniques are also part of the contents of the book.Books on Demand GmbH, Überseering 33, 22297 Hamburg 96 pp. Englisch. N° de réf. du vendeur 9783659239618
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