One of the major issues in the design of SRAMs is the memory access time (or speed of read operation). For having high performance SRAMs, it is essential to take care of the read speed both in the cell-level design and in the design of a clever sense amplifier. Sense amplifiers are one of the most critical circuits in the organization of CMOS memories. Their performance strongly influences both memory access time and overall memory power consumption. High density memories commonly come with increased bit line parasitic capacitance. These large capacitance slow down voltage sensing and makes bit line voltage swings energy-consuming, which result in slower more power hungry memories. Need for larger memory capacity, higher speed, and lower power dissipation.In this work, design of low power high speed sense amplifier for CMOS SRAMs has been done. It has to sense the lowest possible signal swing from the SRAMs bit lines and its response time should be very fast while keeping the power consumption within a tolerable limit. This sense amplifier will be based on latest architectures available in literature and my focus will be to improve the power consumption and response time.
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Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - One of the major issues in the design of SRAMs is the memory access time (or speed of read operation). For having high performance SRAMs, it is essential to take care of the read speed both in the cell-level design and in the design of a clever sense amplifier. Sense amplifiers are one of the most critical circuits in the organization of CMOS memories. Their performance strongly influences both memory access time and overall memory power consumption. High density memories commonly come with increased bit line parasitic capacitance. These large capacitance slow down voltage sensing and makes bit line voltage swings energy-consuming, which result in slower more power hungry memories. Need for larger memory capacity, higher speed, and lower power dissipation.In this work, design of low power high speed sense amplifier for CMOS SRAMs has been done. It has to sense the lowest possible signal swing from the SRAMs bit lines and its response time should be very fast while keeping the power consumption within a tolerable limit. This sense amplifier will be based on latest architectures available in literature and my focus will be to improve the power consumption and response time. N° de réf. du vendeur 9783659242984
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Kartoniert / Broschiert. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Rajput SakshiMs.Sakshi Rajput is working as Assistant Professor in Maharaja SurajmalInstitute of Technology,Delhi.She received B.E.(Hons) in Electronicsand Communication from University of Rajasthan,Jaipur and M.Tech(Hons) in VLSI De. N° de réf. du vendeur 5142475
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Taschenbuch. Etat : Neu. Low Power High Speed Sense Amplifier for CMOS SRAM | Schematic and Analysis | Sakshi Rajput | Taschenbuch | Englisch | LAP Lambert Academic Publishing | EAN 9783659242984 | Verantwortliche Person für die EU: LAP Lambert Academic Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu. N° de réf. du vendeur 106288420
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