An Innovative Approach of Low cost CP-PLL DFT Design: using 1.25 micron meter CMOS Technology - Couverture souple

Tiwari, Ashish

 
9783659248689: An Innovative Approach of Low cost CP-PLL DFT Design: using 1.25 micron meter CMOS Technology
Couverture souple
ISBN 10 : 3659248681 ISBN 13 : 9783659248689
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

This book presents an innovative approach to detect computational fault using design for testability (DFT) of CP-PLL (charge pump phase locked loop) to allow simple digital testing. The proposed structure is useful in mixed signal IC (incorporating both analog and digital block on the same chip) testing. With increasing complexity of mixed signal IC the demand of preparing the low cost testing circuitry also gets increased. Here CP-PLL is taken as the mixed signal IC wherein the proposed method uses the charge pump as stimulus generator and the VCO (voltage controlled oscillator) as measuring device for testing the CP-PLL. It avoids the need of interfacing any foreign component and decreases the area overhead of whole IC. Moreover, testing circuitry is applied at the digital part of the CP-PLL i.e. PFD (phase frequency detector) and the analog part i.e. charge pump; loop filter and VCO are controlled by PFD only. Consequently the efficiency of the testing process avoiding the loading effect at analog node is increased. Fault simulation results indicate that the proposed structure posses high fault coverage of 98.2% and less area overhead of about 3.025%.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

This book presents an innovative approach to detect computational fault using design for testability (DFT) of CP-PLL (charge pump phase locked loop) to allow simple digital testing. The proposed structure is useful in mixed signal IC (incorporating both analog and digital block on the same chip) testing. With increasing complexity of mixed signal IC the demand of preparing the low cost testing circuitry also gets increased. Here CP-PLL is taken as the mixed signal IC wherein the proposed method uses the charge pump as stimulus generator and the VCO (voltage controlled oscillator) as measuring device for testing the CP-PLL. It avoids the need of interfacing any foreign component and decreases the area overhead of whole IC. Moreover, testing circuitry is applied at the digital part of the CP-PLL i.e. PFD (phase frequency detector) and the analog part i.e. charge pump; loop filter and VCO are controlled by PFD only. Consequently the efficiency of the testing process avoiding the loading effect at analog node is increased. Fault simulation results indicate that the proposed structure posses high fault coverage of 98.2% and less area overhead of about 3.025%.

Biographie de l'auteur

Prof. Ashish Tiwari received his M.E. degree in 2012 in VLSI Design.He is working as Assistant Professor in Dept. of ETC, Shri Shankaracharya Technical Campus, Bhilai (INDIA). He is the author of different articles published in various international and national journals and conferences including IEEE.His area of interest lies in back end VLSI,DSP.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
3659248681
ISBN 13 
9783659248689
Reliure
Broché
Nombre de pages
136
Coordonnées du fabricant
non disponible
Personne responsable
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