Systolic Array Based Discrete Wavelet Transform: First Edition - Couverture souple

Hemanth, J.; Chandra Sekhar, C.; Rama Murthy, L.

 
9783659257414: Systolic Array Based Discrete Wavelet Transform: First Edition
Couverture souple
ISBN 10 : 3659257419 ISBN 13 : 9783659257414
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

Now a days due to limitations in communication bandwidth there is more demand for compression in applications like multimedia communication, Television, Video Conferencing etc. This can be done by using DWT(Discrete Wavelet Transform) or DCT (Discrete Cosine Transform). DCT has poor reconstructed image when high compression is performed hence DWT is used. This book presents an implementation of DWT using Systolic architecture in VLSI .This architecture consist of Input delay unit, filter, register bank and control unit. This performs the calculation of high pass and low pass coefficients by using only one multiplier. This architecture has been simulated and implemented in VLSI. The hardware utilization efficiency is more compared to the referred due to FBRA Scheme. The systolic nature of this architecture corresponding to a clock speed of 115.9 MHz has its advantage in Optimizing area, time and power. The architecture is simple, modular, and cascadable for computation of one, or multi-dimensional DWT. Finally comparison of results of Systolic Array architecture and the lifting based architecture is done, which showed that prior is much faster.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Now a days due to limitations in communication bandwidth there is more demand for compression in applications like multimedia communication, Television, Video Conferencing etc. This can be done by using DWT(Discrete Wavelet Transform) or DCT (Discrete Cosine Transform). DCT has poor reconstructed image when high compression is performed hence DWT is used. This book presents an implementation of DWT using Systolic architecture in VLSI .This architecture consist of Input delay unit, filter, register bank and control unit. This performs the calculation of high pass and low pass coefficients by using only one multiplier. This architecture has been simulated and implemented in VLSI. The hardware utilization efficiency is more compared to the referred due to FBRA Scheme. The systolic nature of this architecture corresponding to a clock speed of 115.9 MHz has its advantage in Optimizing area, time and power. The architecture is simple, modular, and cascadable for computation of one, or multi-dimensional DWT. Finally comparison of results of Systolic Array architecture and the lifting based architecture is done, which showed that prior is much faster.

Biographie de l'auteur

Mr. J.Hemanth is working as an Asst. Professor in Dept. of ECE, Vemu IT,P.Kothakota, Chittoor (D), A.P, India, pursued his M.Tech from SVCET, affiliated to JNTUA, Chittoor (D)in the year 2012 and B.Tech from KEC,Kuppam, affiliated to JNTUA, Chittoor (D), A.P, India in the year 2010. His interested areas are VLSI,Image Processing and Radar Systems.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
3659257419
ISBN 13 
9783659257414
Reliure
Broché
Nombre de pages
108
Coordonnées du fabricant
non disponible
Personne responsable
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