Output-Capacitor-Free Low-Dropout Regulators: Analysis and Design: Analysis and Design of High-Performance CMOS Output-Capacitor-Free Low-Dropout Regulators for System-on-Chip - Couverture souple

Zhan, Chenchang; Ki, Wing-Hung

 
9783659291883: Output-Capacitor-Free Low-Dropout Regulators: Analysis and Design: Analysis and Design of High-Performance CMOS Output-Capacitor-Free Low-Dropout Regulators for System-on-Chip
Couverture souple
ISBN 10 : 3659291889 ISBN 13 : 9783659291883
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

Low-dropout regulators (LDRs) are indispensable components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications. Three different topologies: adaptively biased LDRs, adaptively biased LDRs with subthreshold undershoot-reduction, and LDRs with low-quiescent current and high power-supply-rejections are analyzed, designed and verified. They are powerful candidates for supplying different blocks of SoC: analog, mixed-signal, digital, and RF. Design-oriented and in-depth theoretical analysis is presented. With these topologies at hand, a cost-effective power management solution for SoC is easier-than-ever to construct.

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Présentation de l'éditeur

Low-dropout regulators (LDRs) are indispensable components widely used in system-on-chip (SoC) designs to power up noise-sensitive blocks. With the proliferation of portable applications, LDRs are required to have accurate and fast regulation with low quiescent current consumption, compact chip area and without requiring any off-chip capacitors. This research focuses on the analysis and design of high-performance CMOS output-capacitor-free LDRs for SoC power management applications. Three different topologies: adaptively biased LDRs, adaptively biased LDRs with subthreshold undershoot-reduction, and LDRs with low-quiescent current and high power-supply-rejections are analyzed, designed and verified. They are powerful candidates for supplying different blocks of SoC: analog, mixed-signal, digital, and RF. Design-oriented and in-depth theoretical analysis is presented. With these topologies at hand, a cost-effective power management solution for SoC is easier-than-ever to construct.

Biographie de l'auteur

Dr. Chenchang Zhan is a Senior Engineer at Qualcomm Technologies Inc., San Diego, CA. He is an expert in the analysis and design of analog, mixed-signal and power management IC's which are the subjects he authored or co-authored many scientific publications. He is the recipient of Best Paper Awards in IEEE ISIC'2009, EDSSC'2010 and ISCAS'2011.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
3659291889
ISBN 13 
9783659291883
Reliure
Broché
Nombre de pages
144
Coordonnées du fabricant
non disponible
Personne responsable
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