Articles liés à CMOS SRAM Memory Chip Design: High Speed and Low Power

CMOS SRAM Memory Chip Design: High Speed and Low Power - Couverture souple

Rajput, Sakshi

 
9783659320378: CMOS SRAM Memory Chip Design: High Speed and Low Power
Couverture souple
ISBN 10 : 3659320374 ISBN 13 : 9783659320378
Editeur : LAP LAMBERT Academic Publishing, 2013

Synopsis

Static random-access memory (SRAM) continues to be a critical component across a wide range of microelectronics applications from consumer wireless to high-end workstation and microprocessor applications. For almost all fields of applications, semiconductor memory has been a key enabling technology. It is forecasted that embedded memory in SOC designs will cover up to 90% of the total chip area. A representative example is the use of cache memory in microprocessors. The operational speed could be significantly improved by the application of on-chip cache memory Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, toward higher storage densities. This book deals with design of low power static random-access memory cells and peripheral circuits for standalone RAMs, in 350nm focusing on stable operation and reduced leakage current and power dissipation in standby and active modes.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Static random-access memory (SRAM) continues to be a critical component across a wide range of microelectronics applications from consumer wireless to high-end workstation and microprocessor applications. For almost all fields of applications, semiconductor memory has been a key enabling technology. It is forecasted that embedded memory in SOC designs will cover up to 90% of the total chip area. A representative example is the use of cache memory in microprocessors. The operational speed could be significantly improved by the application of on-chip cache memory Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital systems. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, toward higher storage densities. This book deals with design of low power static random-access memory cells and peripheral circuits for standalone RAMs, in 350nm focusing on stable operation and reduced leakage current and power dissipation in standby and active modes.

Biographie de l'auteur

Ms.Sakshi Rajput is working as Assistant Professor in Maharaja Surajmal Institute of Technology,Delhi.She received B.E.(Hons)in Electronics and Communication from University of Rajasthan,Jaipur and M.Tech(Hons)in VLSI Design from Guru Gobind Singh Indraprastha University,Delhi .Her research interest includes Low power VLSI design.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2013
Langue
anglais
ISBN 10 
3659320374
ISBN 13 
9783659320378
Reliure
Broché
Nombre de pages
136
Coordonnées du fabricant
non disponible
Personne responsable
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