Articles liés à Xilinx HDLC Supporting IP over SONET And Checking 16,32Bit...

Xilinx HDLC Supporting IP over SONET And Checking 16,32Bit CRC: XILINX HDLC and CRC Checking - Couverture souple

Mishra, Neeraj

 
9783659341182: Xilinx HDLC Supporting IP over SONET And Checking 16,32Bit CRC: XILINX HDLC and CRC Checking
Couverture souple
ISBN 10 : 3659341185 ISBN 13 : 9783659341182
Editeur : LAP LAMBERT Academic Publishing, 2013

Synopsis

In the present work of Xilinx HDLC controller. HDLC operates at the data link layer of the OSI Model main focus of the is to understand the data link layer and develop a protocol which can offer its services to the layer above it i.e. is the network layer and the layer below it i.e. the physical layer. The function of this protocol controller is to perform a number of separate activities like physical addressing, to check for errors, flow control design of HDLC Controller and simulation design and implement a high performance. This will then be coded in a hardware description language (VHDL). The functioning of the coded design is to be simulated on simulation software (e.g. Model Sim.).After proper simulation, the design is to be synthesized and then translated to a structural architecture in terms of the components on the target FPGA device (Spartan 3) and the perform the post-translate simulation in order to ensure the proper functioning of the design after translation. After the successful simulation of the post-translate model the design is mapped to the existing slices of the FPGA and the post-map model simulated.The objective is to run the programmed FPGA high as possible.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

In the present work of Xilinx HDLC controller. HDLC operates at the data link layer of the OSI Model main focus of the is to understand the data link layer and develop a protocol which can offer its services to the layer above it i.e. is the network layer and the layer below it i.e. the physical layer. The function of this protocol controller is to perform a number of separate activities like physical addressing, to check for errors, flow control design of HDLC Controller and simulation design and implement a high performance. This will then be coded in a hardware description language (VHDL). The functioning of the coded design is to be simulated on simulation software (e.g. Model Sim.).After proper simulation, the design is to be synthesized and then translated to a structural architecture in terms of the components on the target FPGA device (Spartan 3) and the perform the post-translate simulation in order to ensure the proper functioning of the design after translation. After the successful simulation of the post-translate model the design is mapped to the existing slices of the FPGA and the post-map model simulated.The objective is to run the programmed FPGA high as possible.

Biographie de l'auteur

Er. Neeraj Kumar Mishra received his M.Tech degree (HONs EC) from Amity University, India in 2012.His areas of interest are VHDL, DSP, Wireless Communication, Signal Processing & Application etc.And Twelve research Paper Published in various conferences.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2013
Langue
anglais
ISBN 10 
3659341185
ISBN 13 
9783659341182
Reliure
Broché
Nombre de pages
112
Coordonnées du fabricant
non disponible
Personne responsable
KreGa Onlinehandel GmbH
4950000000000
info@krega-onlinehandel.de

Birkenweg 31
Brakel
33034
Allemagne