Mathematical Layout of a Graph Embedding - Couverture souple

Arockiaraj, Micheal; Rajasingh, Indra

 
9783659366611: Mathematical Layout of a Graph Embedding
Couverture souple
ISBN 10 : 3659366617 ISBN 13 : 9783659366611
Editeur : LAP LAMBERT Academic Publishing, 2013

Synopsis

An important feature of an interconnection network is its ability to efficiently simulate programs written for other architectures. Such a simulation problem can be mathematically formulated as graph embedding. Graph embedding is an important technique for studying the computational capabilities of processor interconnection networks and task distributions, which is a recent focus of research in the parallel processing area. The quality of an embedding can be measured by certain cost criteria, namely dilation and wire-length (layout). Dilation is the measure for the communication time needed when simulating one network on another. The layout of a graph embedding arises from the VLSI designs, biological models that deal with cloning and visual stimuli, parallel architecture and structural engineering. In this book we give the techniques to compute the layout of a graph embedding and apply this for certain well known interconnection networks such as circulant networks, hypercubes, folded hypercubes, grid networks and generalized Petersen graphs.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

An important feature of an interconnection network is its ability to efficiently simulate programs written for other architectures. Such a simulation problem can be mathematically formulated as graph embedding. Graph embedding is an important technique for studying the computational capabilities of processor interconnection networks and task distributions, which is a recent focus of research in the parallel processing area. The quality of an embedding can be measured by certain cost criteria, namely dilation and wire-length (layout). Dilation is the measure for the communication time needed when simulating one network on another. The layout of a graph embedding arises from the VLSI designs, biological models that deal with cloning and visual stimuli, parallel architecture and structural engineering. In this book we give the techniques to compute the layout of a graph embedding and apply this for certain well known interconnection networks such as circulant networks, hypercubes, folded hypercubes, grid networks and generalized Petersen graphs.

Biographie de l'auteur

Dr.Micheal Arockiaraj is an Assistant Professor of Mathematics in Loyola College, Chennai. His research interests include study of embedding parameters in interconnection networks and topological indices of chemical graphs. Dr.Indra Rajasingh who is currently a Professor of Mathematics in VIT University, Chennai, India, was his research supervisor.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2013
Langue
anglais
ISBN 10 
3659366617
ISBN 13 
9783659366611
Reliure
Broché
Nombre de pages
164
Coordonnées du fabricant
non disponible
Personne responsable
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