Synopsis
The current process technologies are able to integrate billions of transistors on a single chip and the density of integration is even increasing. To effectively utilize the continuous increase in on-chip area there is a trend towards integration of more and more processing elements e.g. general-purpose processors, DSPs, memories, ASICs, reconfigurable hardware and custom hardware onto a single chip. The continuous increasing demand in number of on-chip resources has lead the SoC researchers to design scalable, modular and efficient on-chip communication infrastructures known as networks on chip (NoC). Design and selection of appropriate architecture, routing algorithm, router micro-architecture and mapping techniques for on-chip communication has a key role in the design and implementation of the complete platform for NoC. This book contributes by presenting two simulation models and then applying these models on some proposed generic as well as application specific efficient, scalable and optimized architectures & routing algorithms for on-chip communication.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
À propos de l?auteur
Sheraz Anjum, PhD: Microelectronics and Solid-State Electronics from Institute of Microelectronics, Graduate University of Chinese Academy of Sciences, Beijing, China. Associate Professor at the Department of Electrical Engineering, COMSATS Institute of Information Technology, Wah Cantt Pakistan.
Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.
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Modeling and Evaluation of Networks on Chip
Edité par
LAP LAMBERT Academic Publishing Apr 2013, 2013
ISBN 10 : 3659383821
ISBN 13 : 9783659383823
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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The current process technologies are able to integrate billions of transistors on a single chip and the density of integration is even increasing. To effectively utilize the continuous increase in on-chip area there is a trend towards integration of more and more processing elements e.g. general-purpose processors, DSPs, memories, ASICs, reconfigurable hardware and custom hardware onto a single chip. The continuous increasing demand in number of on-chip resources has lead the SoC researchers to design scalable, modular and efficient on-chip communication infrastructures known as networks on chip (NoC). Design and selection of appropriate architecture, routing algorithm, router micro-architecture and mapping techniques for on-chip communication has a key role in the design and implementation of the complete platform for NoC. This book contributes by presenting two simulation models and then applying these models on some proposed generic as well as application specific efficient, scalable and optimized architectures & routing algorithms for on-chip communication. 108 pp. Englisch. N° de réf. du vendeur 9783659383823
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Modeling and Evaluation of Networks on Chip
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LAP LAMBERT Academic Publishing, 2013
ISBN 10 : 3659383821
ISBN 13 : 9783659383823
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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Anjum SherazSheraz Anjum, PhD: Microelectronics and Solid-State Electronics from Institute of Microelectronics, Graduate University of Chinese Academy of Sciences, Beijing, China. Associate Professor at the Department of Electrical . N° de réf. du vendeur 5152648
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Modeling and Evaluation of Networks on Chip
Edité par
LAP LAMBERT Academic Publishing, 2013
ISBN 10 : 3659383821
ISBN 13 : 9783659383823
Neuf
Taschenbuch
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
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Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The current process technologies are able to integrate billions of transistors on a single chip and the density of integration is even increasing. To effectively utilize the continuous increase in on-chip area there is a trend towards integration of more and more processing elements e.g. general-purpose processors, DSPs, memories, ASICs, reconfigurable hardware and custom hardware onto a single chip. The continuous increasing demand in number of on-chip resources has lead the SoC researchers to design scalable, modular and efficient on-chip communication infrastructures known as networks on chip (NoC). Design and selection of appropriate architecture, routing algorithm, router micro-architecture and mapping techniques for on-chip communication has a key role in the design and implementation of the complete platform for NoC. This book contributes by presenting two simulation models and then applying these models on some proposed generic as well as application specific efficient, scalable and optimized architectures & routing algorithms for on-chip communication. N° de réf. du vendeur 9783659383823
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Modeling and Evaluation of Networks on Chip
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LAP LAMBERT Academic Publishing Apr 2013, 2013
ISBN 10 : 3659383821
ISBN 13 : 9783659383823
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Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -The current process technologies are able to integrate billions of transistors on a single chip and the density of integration is even increasing. To effectively utilize the continuous increase in on-chip area there is a trend towards integration of more and more processing elements e.g. general-purpose processors, DSPs, memories, ASICs, reconfigurable hardware and custom hardware onto a single chip. The continuous increasing demand in number of on-chip resources has lead the SoC researchers to design scalable, modular and efficient on-chip communication infrastructures known as networks on chip (NoC). Design and selection of appropriate architecture, routing algorithm, router micro-architecture and mapping techniques for on-chip communication has a key role in the design and implementation of the complete platform for NoC. This book contributes by presenting two simulation models and then applying these models on some proposed generic as well as application specific efficient, scalable and optimized architectures & routing algorithms for on-chip communication.Books on Demand GmbH, Überseering 33, 22297 Hamburg 108 pp. Englisch. N° de réf. du vendeur 9783659383823
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Modeling and Evaluation of Networks on Chip
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LAP LAMBERT Academic Publishing, 2013
ISBN 10 : 3659383821
ISBN 13 : 9783659383823
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Taschenbuch. Etat : Neu. Modeling and Evaluation of Networks on Chip | Sheraz Anjum | Taschenbuch | 108 S. | Englisch | 2013 | LAP LAMBERT Academic Publishing | EAN 9783659383823 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu. N° de réf. du vendeur 105964151
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Modeling and Evaluation of Networks on Chip
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LAP LAMBERT Academic Publishing, 2013
ISBN 10 : 3659383821
ISBN 13 : 9783659383823
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