High Performance Comparator Design using Hybrid PTL/CMOS Logic Style - Couverture souple

Sharma, Geetanjali ; Nirmal, Uma

9783659420931: High Performance Comparator Design using Hybrid PTL/CMOS Logic Style

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ISBN 10 : 365942093X ISBN 13 : 9783659420931

Editeur : LAP LAMBERT Academic Publishing, 2013

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�diteur: LAP LAMBERT Academic Publishing
Date d'�dition: 2013
Langue: anglais
ISBN 10: 365942093X
ISBN 13: 9783659420931
Reliure: Broch�
Nombre de pages: 84
Coordonn�es du fabricant: non disponible
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style

Geetanjali Sharma

Edit� par LAP LAMBERT Academic Publishing Sep 2013, 2013

ISBN 10 : 365942093X ISBN 13 : 9783659420931

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Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne

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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1's complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors. 84 pp. Englisch. N� de r�f. du vendeur 9783659420931

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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style

Sharma, Geetanjali

ISBN 10 : 365942093X ISBN 13 : 9783659420931

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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style

Sharma, Geetanjali

ISBN 10 : 365942093X ISBN 13 : 9783659420931

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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style

Sharma, Geetanjali

ISBN 10 : 365942093X ISBN 13 : 9783659420931

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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style

Geetanjali Sharma|Uma Nirmal

Edit� par LAP LAMBERT Academic Publishing, 2013

ISBN 10 : 365942093X ISBN 13 : 9783659420931

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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sharma GeetanjaliMs. Geetanjali Sharma received her Master s degree in VLSI Design and B.Tech degree in Electronics and Communication Engg. from Rajasthan University,India.She is currently working as an Assistant Professor with MSIT,. N� de r�f. du vendeur 385766639

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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style

Geetanjali Sharma

Edit� par LAP LAMBERT Academic Publishing Sep 2013, 2013

ISBN 10 : 365942093X ISBN 13 : 9783659420931

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Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne

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Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1's complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors.VDM Verlag, Dudweiler Landstra�e 99, 66123 Saarbr�cken 84 pp. Englisch. N� de r�f. du vendeur 9783659420931

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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style

Geetanjali Sharma

Edit� par LAP LAMBERT Academic Publishing

ISBN 10 : 365942093X ISBN 13 : 9783659420931

Neuf Taschenbuch

impression � la demande

Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne

�valuation du vendeur 5 sur 5 �toiles

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1's complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors. N� de r�f. du vendeur 9783659420931

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