Articles liés à High Performance Comparator Design using Hybrid PTL/CMOS...
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- ÉditeurLAP LAMBERT Academic Publishing
- Date d'édition2013
- ISBN 10 365942093X
- ISBN 13 9783659420931
- ReliureBroché
- Nombre de pages84
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
Edité par
LAP LAMBERT Academic Publishing Sep 2013
(2013)
ISBN 10 : 365942093X
ISBN 13 : 9783659420931
Neuf
Taschenbuch
Quantité disponible : 2
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Description du livre Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1's complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors. 84 pp. Englisch. N° de réf. du vendeur 9783659420931
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
Edité par
LAP LAMBERT Academic Publishing
ISBN 10 : 365942093X
ISBN 13 : 9783659420931
Neuf
Taschenbuch
Quantité disponible : 1
Vendeur :
Evaluation vendeur
Description du livre Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The main objective of this book is to provide new low power, low area and low power delay product solution for Very Large Scale Integration (VLSI) designers. At circuit level, Hybrid PTL/CMOS logic style gives best results over CMOS only and PTL only. A fine cost-performance ratio comparator design based on modified 1's complement principle and conditional sum adder scheme using Hybrid PTL/CMOS logic style has been proposed in this report and the proposed design has small power dissipation, low power delay product and less area over various parameter ranges. Simulations are based on BSIM 3V3 90nm CMOS technology. It shows an 8-bit comparator of the proposed architecture only needs 154 transistors. N° de réf. du vendeur 9783659420931
Acheter neuf
EUR 39,90
Autre devise
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High Performance Comparator Design using Hybrid PTL/CMOS Logic Style
Edité par
LAP LAMBERT Academic Publishing
(2013)
ISBN 10 : 365942093X
ISBN 13 : 9783659420931
Neuf
Couverture souple
Quantité disponible : > 20
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Evaluation vendeur
Description du livre Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Sharma GeetanjaliMs. Geetanjali Sharma received her Master s degree in VLSI Design and B.Tech degree in Electronics and Communication Engg. from Rajasthan University,India.She is currently working as an Assistant Professor with MSIT,. N° de réf. du vendeur 385766639
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