The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform.
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Dr.J. Bhaumik is working as an Asoc. Prof. in the Dept. of ECE, HIT. He obtained his PhD degree from IIT Kharagpur. He received his B.Tech & M.Tech from CU. His research areas: VLSI Design & Cryptography.Mr.A.S.Das is working as a JRF at Sidho-Kanho Birsha University. He did his M.Tech in ECE from WBUT. His research areas:ECC,Optical comm & VLSI.
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Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform. 64 pp. Englisch. N° de réf. du vendeur 9783659457265
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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Bhaumik JaydebDr.J. Bhaumik is working as an Asoc. Prof. in the Dept. of ECE, HIT. He obtained his PhD degree from IIT Kharagpur. He received his B.Tech & M.Tech from CU. His research areas: VLSI Design & Cryptography.Mr.A.S.Das is w. N° de réf. du vendeur 5157270
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Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 64 pp. Englisch. N° de réf. du vendeur 9783659457265
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Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - The modern communications systems become faster day by day. Errors almost inevitably occur during the transmission, storage or processing of information, because of noise and interference in communication channels, or imperfections in storage media. Therefore, the detection and correction of errors in information have become very important issue. Reed-Solomon (RS) codes are non-binary, cyclic error correcting codes which are very much effective for the detection and correction of burst errors. RS codes are defined over Galois field. The encoder appends parity symbols to the data using a predetermined algorithm before transmission. Decoder detects and corrects errors. VLSI design creates a flexible and high degree of parallelism for implementing the RS codes. The purpose of this thesis is to design and implement a programmable RS encoder and decoder on an FPGA platform. In this work, a modified architecture for a programmable RS encoder and decoder has been proposed. Employing the proposed scheme, RS codes can be generated and decoded for different generator polynomials. Also an RS (255, 251) encoder and decoder have been implemented on an FPGA platform. N° de réf. du vendeur 9783659457265
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Vendeur : preigu, Osnabrück, Allemagne
Taschenbuch. Etat : Neu. Programmable Reed-Solomon Codec | Design and Implementation | Jaydeb Bhaumik (u. a.) | Taschenbuch | 64 S. | Englisch | 2013 | LAP LAMBERT Academic Publishing | EAN 9783659457265 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. N° de réf. du vendeur 105619018
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