Design of 5.5 GHz Highly Linear CMOS Low Noise Amplifier - Couverture souple

A. Talukdar, Fazal; Kumar, Ram

 
9783659495939: Design of 5.5 GHz Highly Linear CMOS Low Noise Amplifier
Couverture souple
ISBN 10 : 365949593X ISBN 13 : 9783659495939
Editeur : LAP LAMBERT Academic Publishing, 2013

Synopsis

Recently, telecommunication system requires high performance, low noise, low power and high linear RF circuits. Since the digital modulation design requires highly linear front end circuits, the linearity requirement of the LNA becomes more rigorous. Due to possible large interference signal tones at the receiver end along with the carrier, LNA is expected to provide high linearity, thus preventing the intermodulation tones created by the interference signal from corrupting the carrier signal. The research focuses on designing a LNA which achieves high linearity without sacrificing any of its specifications of gain and Noise Figure (NF). The project focused on designing a 5.5 GHz linear LNA using a standard UMC.18um technology. The LNA employed inductive source degeneration topology with on chip passive spiral inductor. Employing the body biasing technique with post distortion scheme not only achieve high linearity, but also minimizes the degradation of gain, noise figure and power consumption. The simulation results show that CMOS tech has the capability to achieve a 5.5 GHz LNA. The LNA draws a 10.8mw power on 1.8V power supply while achieve gain of 11.4dB IIP3 of 9.20dBm

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Présentation de l'éditeur

Recently, telecommunication system requires high performance, low noise, low power and high linear RF circuits. Since the digital modulation design requires highly linear front end circuits, the linearity requirement of the LNA becomes more rigorous. Due to possible large interference signal tones at the receiver end along with the carrier, LNA is expected to provide high linearity, thus preventing the intermodulation tones created by the interference signal from corrupting the carrier signal. The research focuses on designing a LNA which achieves high linearity without sacrificing any of its specifications of gain and Noise Figure (NF). The project focused on designing a 5.5 GHz linear LNA using a standard UMC.18um technology. The LNA employed inductive source degeneration topology with on chip passive spiral inductor. Employing the body biasing technique with post distortion scheme not only achieve high linearity, but also minimizes the degradation of gain, noise figure and power consumption. The simulation results show that CMOS tech has the capability to achieve a 5.5 GHz LNA. The LNA draws a 10.8mw power on 1.8V power supply while achieve gain of 11.4dB IIP3 of 9.20dBm

Biographie de l'auteur

Dr.Fazal A Talukdar obtained his Bachelor of Engineering (Hons) from Regional Engineering College, Silchar (now, NIT Silchar) in 1987. He obtained his MTech in 1993 and PhD in 2002-03 from Indian Institute of Technology Delhi and Jadavpur University respectively.He is a working as professor in ece department nit silchar.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2013
Langue
anglais
ISBN 10 
365949593X
ISBN 13 
9783659495939
Reliure
Broché
Nombre de pages
76
Coordonnées du fabricant
non disponible
Personne responsable
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