UDSM CMOS Circuits: Delay & Power Models - Couverture souple

Samanta, Jagannath

 
9783659523038: UDSM CMOS Circuits: Delay & Power Models
Couverture souple
ISBN 10 : 3659523038 ISBN 13 : 9783659523038
Editeur : LAP LAMBERT Academic Publishing, 2014

Synopsis

A simple and accurate delay model is proposed for Ultra Deep Sub-micron CMOS circuits (CMOS Inverter, NAND2, NOR2 etc) based on nth power law when the channel length is less than the 90nm. All the parameters are taken from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects i.e. Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), Substrate Current Induced Body Effect (SCBE), Drain-Induced Threshold Shift (DITS), which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 inputs CMOS NAND & NOR gates. Our result is better than simulation result with respect to both quality and estimation time. This work also thoroughly described the delay dependence on different parameters such as channel length, Load Capacitance, Supply voltage, Transition time, Velocity Saturation Coefficient, Threshold Voltage, Load Resistance, Width variation etc. This also explained the different power models for the estimation of UDSM circuts.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

A simple and accurate delay model is proposed for Ultra Deep Sub-micron CMOS circuits (CMOS Inverter, NAND2, NOR2 etc) based on nth power law when the channel length is less than the 90nm. All the parameters are taken from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects i.e. Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), Substrate Current Induced Body Effect (SCBE), Drain-Induced Threshold Shift (DITS), which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 inputs CMOS NAND & NOR gates. Our result is better than simulation result with respect to both quality and estimation time. This work also thoroughly described the delay dependence on different parameters such as channel length, Load Capacitance, Supply voltage, Transition time, Velocity Saturation Coefficient, Threshold Voltage, Load Resistance, Width variation etc. This also explained the different power models for the estimation of UDSM circuts.

Biographie de l'auteur

J Samanta,currently working as Assistant Professor in the dept. of ECE at HIT, Haldia,India. He has received his B.Tech & M.Tech Degree from WBUT Kolkata. He has awarded Gold Medal during M.Tech course. His research interests include Error Control Codes,Digital VLSI Design, MOSFET modeling. He has more than 14 international publications.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2014
Langue
anglais
ISBN 10 
3659523038
ISBN 13 
9783659523038
Reliure
Broché
Nombre de pages
96
Coordonnées du fabricant
non disponible
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