Design Methodology for highly Reliable Digital ASIC Designs: Applied to Network-Centric System Middleware Switch Processor - Couverture souple

Petrovic, Vladimir

 
9783659534157: Design Methodology for highly Reliable Digital ASIC Designs: Applied to Network-Centric System Middleware Switch Processor
Couverture souple
ISBN 10 : 3659534153 ISBN 13 : 9783659534157
Editeur : LAP LAMBERT Academic Publishing, 2014

Synopsis

In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial ASIC technologies in space and safety-critical applications. The most important challenges are: 1. Radiation-hardened technologies are expensive (qualification and quality requirements are severe) and commercially not attractive (small volume production). 2. There is no standard integrated framework of circuit design techniques that provides simultaneous SEU, SET, and SEL fault-tolerance. 3. There is no standard design automation flow for fault-tolerant digital ASICs and SOCs. This book presents a design methodology for fault-tolerant ASIC that is based on redundant circuits with latchup protection and additional implementation steps during logic synthesis and layout generation. The proposed design approach provides the ASICs immune to the upsets, transients, and latchup faults by combining and integrating different fault-tolerant techniques in a carefully designed procedure.

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Présentation de l'éditeur

In spite of the huge research efforts and respectable scientific achievements, there are still challenges regarding the use of commercial ASIC technologies in space and safety-critical applications. The most important challenges are: 1. Radiation-hardened technologies are expensive (qualification and quality requirements are severe) and commercially not attractive (small volume production). 2. There is no standard integrated framework of circuit design techniques that provides simultaneous SEU, SET, and SEL fault-tolerance. 3. There is no standard design automation flow for fault-tolerant digital ASICs and SOCs. This book presents a design methodology for fault-tolerant ASIC that is based on redundant circuits with latchup protection and additional implementation steps during logic synthesis and layout generation. The proposed design approach provides the ASICs immune to the upsets, transients, and latchup faults by combining and integrating different fault-tolerant techniques in a carefully designed procedure.

Biographie de l'auteur

Vladimir Petrovic, Dr.-Ing. Microelectronics, Brandenburg University of Technology, Cottbus, Germany (2013). Research areas are aerospace microelectronics, radiation effects on microelectronics, development of techniques for radiation effects mitigation on system and circuit level. Currently he is scientist at IHP GmbH, Frankfurt (Oder), Germany

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2014
Langue
anglais
ISBN 10 
3659534153
ISBN 13 
9783659534157
Reliure
Broché
Nombre de pages
252
Coordonnées du fabricant
non disponible
Personne responsable
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