Process Variation Tolerant VLSI Designs - Couverture souple

Mahor Vikas

9783659648946: Process Variation Tolerant VLSI Designs

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ISBN 10 : 3659648949 ISBN 13 : 9783659648946

Editeur : LAP Lambert Academic Publishing, 2014

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Les portails dynamiques ont �t� un excellent choix dans la conception de modules haute performance dans les microprocesseurs modernes. La seule limitation des portails dynamiques est leur marge de bruit relativement faible par rapport � celle des portes CMOS standard. Traditionnellement, ce probl�me a �t� r�solu en utilisant un circuit de gardien pMOS qui compense le courant de fuite du r�seau nMOS d�roulant. Dans les nœuds technologiques ant�rieurs, le circuit gardien pourrait am�liorer la fiabilit� des portes dynamiques avec une p�nalit� de performance mineure. Cependant, les tendances agressives de la technologie CMOS ainsi que les niveaux croissants de variations de processus ont r�duit l'efficacit� de l'approche traditionnelle Keeper. Ce probl�me est plus grave dans les portes dynamiques � large ventilateur en raison du grand nombre de dispositifs nMOS qui fuient connect�s au nœud dynamique. Dans ce travail, une porte OU dynamique large tol�rante aux variations de processus avec deux nouveaux mod�les de gardien est propos�e qui sont capables de r�duire la controverse entre le gardien et le PDN et donc capable de r�duire la dissipation de puissance et le retard.

Les informations fournies dans la section � Synopsis � peuvent faire r�f�rence � une autre �dition de ce titre.

�diteur: LAP Lambert Academic Publishing
Date d'�dition: 2014
Langue: anglais
ISBN 10: 3659648949
ISBN 13: 9783659648946
Reliure: Broch�
Nombre de pages: 80
Coordonn�es du fabricant: non disponible
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Process Variation Tolerant VLSI Designs

Vikas Mahor

Edit� par LAP LAMBERT Academic Publishing Dez 2014, 2014

ISBN 10 : 3659648949 ISBN 13 : 9783659648946

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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. 80 pp. Englisch. N� de r�f. du vendeur 9783659648946

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Process Variation Tolerant VLSI Designs

Vikas Mahor

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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Mahor VikasVikas Mahor, received the B.Tech. degree in electronics engineering from the Rajeev Gandhi Technical University, Bhopal, in 2007. In July 2012, he has been awarded with an M. Tech. degree in VLSI Design from Indian Institu. N� de r�f. du vendeur 5170936

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Process Variation Tolerant VLSI Designs

Vikas Mahor

Edit� par LAP LAMBERT Academic Publishing Dez 2014, 2014

ISBN 10 : 3659648949 ISBN 13 : 9783659648946

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Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay.VDM Verlag, Dudweiler Landstra�e 99, 66123 Saarbr�cken 80 pp. Englisch. N� de r�f. du vendeur 9783659648946

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Process Variation Tolerant VLSI Designs : Highly Robust and Process Variation Tolerant CMOS Dynamic Logic Designs

Vikas Mahor

Edit� par LAP LAMBERT Academic Publishing, 2014

ISBN 10 : 3659648949 ISBN 13 : 9783659648946

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Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this work a process variation tolerant wide fan-in dynamic OR gate with two new keeper designs is proposed which are capable of reducing the contention between the keeper and PDN and hence capable of reducing the power dissipation and delay. N� de r�f. du vendeur 9783659648946

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