Design of Magnitude Comparator Using Reversible Logic Gates - Couverture souple

Name: Design of Magnitude Comparator Using Reversible Logic Gates
Author: Karunamurthi, Saranya; Thangavel, Saranya; Boopalan, Saravana Priya
ISBN: 9783659796067

Karunamurthi, Saranya ; Thangavel, Saranya ; Boopalan, Saravana Priya

9783659796067: Design of Magnitude Comparator Using Reversible Logic Gates

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ISBN 10 : 3659796069 ISBN 13 : 9783659796067

Editeur : LAP LAMBERT Academic Publishing, 2018

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A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional.

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�diteur: LAP LAMBERT Academic Publishing
Date d'�dition: 2018
Langue: anglais
ISBN 10: 3659796069
ISBN 13: 9783659796067
Reliure: Broch�
Nombre de pages: 60
Coordonn�es du fabricant: non disponible
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Design of Magnitude Comparator Using Reversible Logic Gates

Saranya Karunamurthi

Edit� par LAP LAMBERT Academic Publishing Sep 2018, 2018

ISBN 10 : 3659796069 ISBN 13 : 9783659796067

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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional. 60 pp. Englisch. N� de r�f. du vendeur 9783659796067

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Design of Magnitude Comparator Using Reversible Logic Gates

Saranya Karunamurthi

Edit� par LAP LAMBERT Academic Publishing, 2018

ISBN 10 : 3659796069 ISBN 13 : 9783659796067

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Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional. N� de r�f. du vendeur 9783659796067

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Design of Magnitude Comparator Using Reversible Logic Gates

Saranya Karunamurthi|Saranya Thangavel|Saravana Priya Boopalan

Edit� par LAP LAMBERT Academic Publishing, 2018

ISBN 10 : 3659796069 ISBN 13 : 9783659796067

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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Karunamurthi SaranyaK. Saranya, is a Assistant Professor, Department of EEE in Dr. Mahalingam College of Engineering & Technology, Pollachi, Tamil Nadu. India. She completed her M.E in department of Applied Electronics at Government . N� de r�f. du vendeur 385769389

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Design of Magnitude Comparator Using Reversible Logic Gates

Karunamurthi, Saranya/ Thangavel, Saranya/ Boopalan, Saravana Priya

Edit� par LAP LAMBERT Academic Publishing, 2018

ISBN 10 : 3659796069 ISBN 13 : 9783659796067

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Paperback. Etat : Brand New. 60 pages. 8.66x5.91x0.14 inches. In Stock. N� de r�f. du vendeur 3659796069

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Design of Magnitude Comparator Using Reversible Logic Gates

Saranya Karunamurthi

Edit� par LAP LAMBERT Academic Publishing Sep 2018, 2018

ISBN 10 : 3659796069 ISBN 13 : 9783659796067

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Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne

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Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -A need for low power ICs arises to keep the power density of ICs within tolerable limits. While the power dissipation increases linearly with advanced version processors, the power density also increases exponentially, because of the ever-shrinking size of the integrated circuits. Reversible logic is emerging as an important research area in the recent years due to its ability to reduce power dissipation, which is the main requirement in low power digital design.In our proposed method reversible comparator based on CMOS logic circuit is designed using reversible gates. In this design we try to reduce optimization parameters like number of constant inputs, garbage outputs, and quantum cost. The experimental results obtained for implementation in CADENCE EDA 180nm technology shows the considerable reduction in terms of Power Delay Product in comparison with the comparator designed in conventional.VDM Verlag, Dudweiler Landstra�e 99, 66123 Saarbr�cken 60 pp. Englisch. N� de r�f. du vendeur 9783659796067

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