Simple Processors for Executing Scalar/Vector/ Matrix Instructions: Design, Implementation, and Performance Evaluation - Couverture souple

Elsayed, Elsayed; Soliman, Mostafa

 
9783659832260: Simple Processors for Executing Scalar/Vector/ Matrix Instructions: Design, Implementation, and Performance Evaluation
Couverture souple
ISBN 10 : 365983226X ISBN 13 : 9783659832260
Editeur : LAP LAMBERT Academic Publishing, 2016

Synopsis

Nowadays, data-parallel applications, which include scientific and engineering, multimedia, network, security, etc., are growing in importance and demanding increased performance from hardware. On the other hand, the exponential growth in the fabrication technology and the continuous improvements in transistor density have allowed tens of billions of transistors to be integrated onto one single chip. Thus, this book proposes three microarchitectures for matrix processors architectures that exploit this huge number of transistors to improve the performance of data-parallel applications: simple matrix processor (SMP), simple super-matrix processor (SSMP), and multithreaded simple super-matrix processor (ThrSSMP). In addition, this book explains in details the implementation of our proposed designs for SMP, SSMP, and ThrSSMP using VHDL targeting FPGA Virtex-6, XC6VLX550T-2FF1760 device. Moreover, the performances of SMP/SSMP/ThrSSMP are evaluated on some vector/matrix kernels from basic linear algebra subprograms(BLAS).

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Nowadays, data-parallel applications, which include scientific and engineering, multimedia, network, security, etc., are growing in importance and demanding increased performance from hardware. On the other hand, the exponential growth in the fabrication technology and the continuous improvements in transistor density have allowed tens of billions of transistors to be integrated onto one single chip. Thus, this book proposes three microarchitectures for matrix processors architectures that exploit this huge number of transistors to improve the performance of data-parallel applications: simple matrix processor (SMP), simple super-matrix processor (SSMP), and multithreaded simple super-matrix processor (ThrSSMP). In addition, this book explains in details the implementation of our proposed designs for SMP, SSMP, and ThrSSMP using VHDL targeting FPGA Virtex-6, XC6VLX550T-2FF1760 device. Moreover, the performances of SMP/SSMP/ThrSSMP are evaluated on some vector/matrix kernels from basic linear algebra subprograms(BLAS).

Biographie de l'auteur

Elsayed A. Elsayed is an assistant lecturer at Faculty of Engineering, Aswan University, Egypt. He received his master degree in Computer Science and Engineering in 2014. He is interested in computer architecture, parallel processing, vector/matrix processing, multi/many-core, and VHDL/FPGA implementations.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2016
Langue
anglais
ISBN 10 
365983226X
ISBN 13 
9783659832260
Reliure
Broché
Nombre de pages
224
Coordonnées du fabricant
non disponible
Personne responsable
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