Design and Development of Network Protocol in FPGA - Couverture souple

Dembrani, Mahesh; Patel, Vinit; Jayaswal, Anupkumar

 
9783659880803: Design and Development of Network Protocol in FPGA
Couverture souple
ISBN 10 : 3659880809 ISBN 13 : 9783659880803
Editeur : LAP LAMBERT Academic Publishing, 2016

Synopsis

The increasing popularity of the Internet stimulates an explosive growth of the data transmitted on the Internet as well as the dramatic increase of the transmission speeds. As a result the TCP/IP processing has become a bottleneck. Traditional software based TCP/IP processing on general purpose processors (GPPs) is no longer able to keep pace with network wire speeds. Consequently, there is an urgent need to design performance-critical TCP/IP functions as special units to accelerate the processing speeds and to offload the processing tasks from GPPs. Such functional units performing micro-level functions can be implemented on field – programmable gate arrays (FPGAs.) FPGAs as programmable hardware devices are particularly suitable to encompass both high processing speeds and flexibility to meet the quickly changing Internet. A challenge in designing the TCP/IP function is that the demand for advanced services requires the network devices to support a wide range of application and protocols; however this application and protocols are constantly evolving.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

The increasing popularity of the Internet stimulates an explosive growth of the data transmitted on the Internet as well as the dramatic increase of the transmission speeds. As a result the TCP/IP processing has become a bottleneck. Traditional software based TCP/IP processing on general purpose processors (GPPs) is no longer able to keep pace with network wire speeds. Consequently, there is an urgent need to design performance-critical TCP/IP functions as special units to accelerate the processing speeds and to offload the processing tasks from GPPs. Such functional units performing micro-level functions can be implemented on field – programmable gate arrays (FPGAs.) FPGAs as programmable hardware devices are particularly suitable to encompass both high processing speeds and flexibility to meet the quickly changing Internet. A challenge in designing the TCP/IP function is that the demand for advanced services requires the network devices to support a wide range of application and protocols; however this application and protocols are constantly evolving.

Biographie de l'auteur

Mr. Mahesh B Dembrani has obtained his Master of Engineering in Digital Electronics from Amravati University, Amravati. He has 10 Years of teaching and research experience. Presently he is working on Signal Processing with special focus on medical and communication applications.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2016
Langue
anglais
ISBN 10 
3659880809
ISBN 13 
9783659880803
Reliure
Broché
Nombre de pages
56
Coordonnées du fabricant
non disponible
Personne responsable
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