CMOS VLSI LOW-POWER DESIGN: DESIGN METHODOLOGY AND IMPLEMENTATION OF LOW-POWER ASYNCHRONOUS VITERBI DECODERS FOR WIRELESS APPLICATIONS - Couverture souple

ELKAWOKGY, MOHAMED

 
9783838301280: CMOS VLSI LOW-POWER DESIGN: DESIGN METHODOLOGY AND IMPLEMENTATION OF LOW-POWER ASYNCHRONOUS VITERBI DECODERS FOR WIRELESS APPLICATIONS
Couverture souple
ISBN 10 : 3838301285 ISBN 13 : 9783838301280
Editeur : LAP LAMBERT Academic Publishing, 2009

Synopsis

Power dissipation is a critical parameter in digital design for the implementation of high performance portable, battery operated systems, such as wireless communications systems. Clocked or synchronous digital designs consume a significant amount of power associated with coordinating the operation of millions of transistors at GHz clock rates. Besides, the operating speed of such systems is limited by the slowest functional logic unit. By contrast, asynchronous designs are active only when doing useful work, enabling considerable savings in power and operating at the average speed of all components. Yet, the overhead associated with the asynchronous control units implementing the handshaking protocol, in terms of silicon area, speed and power, as well as the lack of Computer Aided Design (CAD) tools for use in such designs have limited the use of asynchronous techniques. In this book, the author describes the concept and challenges of asynchronous VLSI CMOS circuit design and presents a complete design methodology to overcome such challenges via the design and implementation of a 64-state, 1/2-rate Viterbi decoder suitable for wireless communications applications.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Power dissipation is a critical parameter in digital design for the implementation of high performance portable, battery operated systems, such as wireless communications systems. Clocked or synchronous digital designs consume a significant amount of power associated with coordinating the operation of millions of transistors at GHz clock rates. Besides, the operating speed of such systems is limited by the slowest functional logic unit. By contrast, asynchronous designs are active only when doing useful work, enabling considerable savings in power and operating at the average speed of all components. Yet, the overhead associated with the asynchronous control units implementing the handshaking protocol, in terms of silicon area, speed and power, as well as the lack of Computer Aided Design (CAD) tools for use in such designs have limited the use of asynchronous techniques. In this book, the author describes the concept and challenges of asynchronous VLSI CMOS circuit design and presents a complete design methodology to overcome such challenges via the design and implementation of a 64-state, 1/2-rate Viterbi decoder suitable for wireless communications applications.

Biographie de l'auteur

Dr. Mohamed Kawokgy is a senior design engineer at Intel Corporation. He received his B.Sc. degree at University of Alexandria, Egypt, in 2001. He received his M.A.Sc. and Ph.D. degrees, in VLSI design, at University of Toronto, Canada, in 2003 and 2007, respectively. Dr. Kawokgy held a senior ASIC design engineering position at AMD in 2007.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2009
Langue
anglais
ISBN 10 
3838301285
ISBN 13 
9783838301280
Reliure
Broché
Nombre de pages
120
Coordonnées du fabricant
non disponible
Personne responsable
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