Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits - Couverture souple

Akl, Charbel

 
9783838307329: Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits
Couverture souple
ISBN 10 : 3838307321 ISBN 13 : 9783838307329
Editeur : LAP Lambert Academic Publishing, 2009

Synopsis

The semiconductor industry has been following Moore?s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

The semiconductor industry has been following Moore?s law over the past five decades due to the continuous CMOS process technology scaling. This scaling has led to reduced integrated circuit cost, higher integration density and better design performance. On the other hand, many new design challenges have been introduced due to scaling, and these chanllenges become more significant when migrating from one technology node to a newer one with smaller feature size. This book presents seven newly developped circuit and interconnect design methods for nanometer CMOS VLSI designs. The first four methods target issues in global on-chip signaling, on-chip busses, and clock signal distribution. Chapters six and seven of this book present circuit techniques for low-power high- speed digital circuits and high fan-in logic design. The last method presented in this book deals with the mode transition latency and energy overheads in the power-gated low-power designs.

Biographie de l'auteur

Charbel Akl received a M.S. in Computer Engineering from University of Balamand, Lebanon, in 2004, and a PhD in Computer Engineering from University of Louisiana at Lafayette in 2008. After graduation, he joined Intel Corporation where he is currently working on the design and implementation of low power microprocessors.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP Lambert Academic Publishing
Date d'édition
2009
Langue
anglais
ISBN 10 
3838307321
ISBN 13 
9783838307329
Reliure
Broché
Nombre de pages
132
Coordonnées du fabricant
non disponible
Personne responsable
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Autres éditions populaires du même titre

9786208480622: Cost-effective Methods for High-speed Nanometer CMOS VLSI Design: Interconnect and Circuits. 2nd Edition

Edition présentée

ISBN 10 :  6208480620 ISBN 13 :  9786208480622
Editeur : LAP LAMBERT Academic Publishing, 2025
Couverture souple