Testing Chips with Mesh-Based Network-on-Chip - Couverture souple

Amory, Alexandre

 
9783838321615: Testing Chips with Mesh-Based Network-on-Chip
Couverture souple
ISBN 10 : 3838321618 ISBN 13 : 9783838321615
Editeur : LAP Lambert Academic Publishing, 2009

Synopsis

Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers hide the NoC from the rest of the test architecture, thus, the cores and the test equipment work exactly like they would work in a conventional test architecture. Thus, the proposed wrapper is compatible with previous approaches, like the IEEE Std. 1500. The test scheduling optimizes the chip test length without requiring full knowledge of the NoC, contributing to the generality of the proposed test methodology. Several benchmarks are applied to the conventional and to the proposed test approaches to compare the resulting chip test length and silicon area overhead.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Global interconnect solutions based on long wires, like buses, are being replaced by solutions based on shared and segmented wires, like Networks-on-Chip (NoCs), to reduce the cost of global interconnect. A conventional Test Access Mechanism (TAM), which consists of long wires, is also subject to these problems. For this reason, this book studies the reuse of on-chip networks for test data transportation, avoiding dedicated TAMs. This book presents an overall test methodology for NoC-based SoCs which consists of steps to build optimized test wrappers and test scheduling. The test wrappers hide the NoC from the rest of the test architecture, thus, the cores and the test equipment work exactly like they would work in a conventional test architecture. Thus, the proposed wrapper is compatible with previous approaches, like the IEEE Std. 1500. The test scheduling optimizes the chip test length without requiring full knowledge of the NoC, contributing to the generality of the proposed test methodology. Several benchmarks are applied to the conventional and to the proposed test approaches to compare the resulting chip test length and silicon area overhead.

Biographie de l'auteur

Alexandre received the degree of Ph.D. in Computer Science from the UFRGS University, Brazil, in 2007. Marcelo received the degree of Ph.D. in Electrical Engineer from INPG, France, in 1994. Fernando received the degree of Ph.D. in Electrical Engineer from LIRMM, France, in 1994.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP Lambert Academic Publishing
Date d'édition
2009
Langue
anglais
ISBN 10 
3838321618
ISBN 13 
9783838321615
Reliure
Broché
Nombre de pages
172
Coordonnées du fabricant
non disponible
Personne responsable
KreGa Onlinehandel GmbH
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