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Celator: Design and development of a reconfigurable cryptographic co-processor - Couverture souple

Fronte, Daniele

 
9783838334882: Celator: Design and development of a reconfigurable cryptographic co-processor
Couverture souple
ISBN 10 : 3838334884 ISBN 13 : 9783838334882
Editeur : LAP Lambert Academic Publishing, 2010

Synopsis

Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more flexibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) or Data Encryption Standard (DES). Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the flexible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other securitycircuits.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Nowadays hi-tech secure products need more services and more security. Furthermore the corresponding market is now oriented towards more flexibility. In this thesis we propose as novel solution a Multi-algorithm Cryptographic Co-processor called Celator. Celator is able to encrypt or decrypt data blocks using private key encryption algorithms such as Advanced Encryption Standard (AES) or Data Encryption Standard (DES). Moreover Celator allows condensing data using the Secure Hash Algorithms (SHA). These algorithms are frequently implemented in hi-tech secure products in software or in hardware mode. Celator belongs to the class of the flexible hardware implementations, and allows an user implementing its own cryptographic algorithm under specific conditions. Celator architecture is based on a 4x4 Processing Elements (PE) systolic array, a Controller with a Finite State Machine (FSM) and a local memory. Data are encrypted or decrypted by the PE array. This thesis presents Celator architecture, as well as its AES, DES, and SHA basic operations. Celator performances are then given and compared to other securitycircuits.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP Lambert Academic Publishing
Date d'édition
2010
Langue
anglais
ISBN 10 
3838334884
ISBN 13 
9783838334882
Reliure
Broché
Nombre de pages
108
Coordonnées du fabricant
non disponible
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