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Designing an 8-bit CMOS Low Glitch Digital-to-Analog Converter: Concept, Analysis and Layout of an Current Steering DAC - Couverture souple

Sarkar, Santanu

 
9783838390826: Designing an 8-bit CMOS Low Glitch Digital-to-Analog Converter: Concept, Analysis and Layout of an Current Steering DAC
Couverture souple
ISBN 10 : 3838390822 ISBN 13 : 9783838390826
Editeur : LAP LAMBERT Academic Publishing, 2010

Synopsis

Digital-to-Analog Converters (DAC) are used to convert the digital inputs back to the analog signals. For any mixed signal system the ADC and DAC are the two most important building blocks. The demand for-high speed, low cost and low power DACs are sharply increasing, with the advancement of the modern telecommunication systems. In present scenario for VLSI design, CMOS technology is widely preferred for high packing density and low cost. In this presentation the design of an 8-bit DAC in CMOS Current Steering Architecture has been discussed. For better understanding the concept of the architecture has been presented with figure and conceptual diagrams. The design and layout of the DAC has been discussed with simulation and post layout simulation results. At the end the measured results are also reported with a discussion on limitations and future scopes.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Digital-to-Analog Converters (DAC) are used to convert the digital inputs back to the analog signals. For any mixed signal system the ADC and DAC are the two most important building blocks. The demand for-high speed, low cost and low power DACs are sharply increasing, with the advancement of the modern telecommunication systems. In present scenario for VLSI design, CMOS technology is widely preferred for high packing density and low cost. In this presentation the design of an 8-bit DAC in CMOS Current Steering Architecture has been discussed. For better understanding the concept of the architecture has been presented with figure and conceptual diagrams. The design and layout of the DAC has been discussed with simulation and post layout simulation results. At the end the measured results are also reported with a discussion on limitations and future scopes.

Biographie de l'auteur

Santanu Sarkar, Research Scholar: E and ECE Department, IIT Kharagpur, India. Completed his MS in 2009 in Microelectronics and VLSI Design from the E&ECE Department of IIT Kharagpur, India.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2010
Langue
anglais
ISBN 10 
3838390822
ISBN 13 
9783838390826
Reliure
Broché
Nombre de pages
112
Coordonnées du fabricant
non disponible
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