Verification and Synthesis of Digital Circuits: High-level Synthesis and Equivalence Checking - Couverture souple

Karfa, Chandan; Sarkar, Dipankar; Mandal, Chittaranjan

Couverture souple

ISBN 10 : 3838398130 ISBN 13 : 9783838398136

Editeur : LAP Lambert Academic Publishing, 2010

Synopsis

Advances in VLSI technology have enabled its deployment into complex circuits. Synthesis flow of such circuits comprises various phases where each phase performs the task algorithmically providing for ingenious interventions of experts. The gap between the original behaviour and the finally synthesized circuit is too wide to be analyzed by any reasoning mechanism. The validation tasks, therefore, must be planned to go hand-in-hand with each phase of synthesis with scope to handle the special characteristics of each synthesis sub-task separately. This book is concerned with hand-in-hand verification and (high-level) synthesis of digital circuits. The verification problem is formulated as equivalence checking between two finite state machines with data-paths (FSMD). The difficulties of each phase are identified and the verification methods based on equivalence of two FSMDs have been formulated accordingly. A high-level synthesis tool, called structured architecture synthesis tool (SAST), has been developed which support hand-in-hand synthesis and verification.

A propos du livre

À propos des auteurs

All authors are with the Department of Computer Science and Engineering, IIT Kharagpur. Chandan Karfa (pictured) is a senior PhD student supported by a Microsoft Research India PhD Fellowship. Dipankar Sarkar and Chittaranjan Mandal are faculty members. The authors are active in CAD for synthesis and verification of digital circuits and systems.

All authors are with the Department of Computer Science and Engineering, IIT Kharagpur. Chandan Karfa (pictured) is a senior PhD student supported by a Microsoft Research India PhD Fellowship. Dipankar Sarkar and Chittaranjan Mandal are faculty members. The authors are active in CAD for synthesis and verification of digital circuits and systems.

All authors are with the Department of Computer Science and Engineering, IIT Kharagpur. Chandan Karfa (pictured) is a senior PhD student supported by a Microsoft Research India PhD Fellowship. Dipankar Sarkar and Chittaranjan Mandal are faculty members. The authors are active in CAD for synthesis and verification of digital circuits and systems.

Détails de l'édition

• Éditeur: LAP Lambert Academic Publishing
• Date d'édition: 2010
• Langue: anglais
• ISBN 10: 3838398130
• ISBN 13: 9783838398136
• Reliure: Broché
• Nombre de pages: 204
• Coordonnées du fabricant: non disponible
• Personne responsable: KreGa Onlinehandel GmbH; 4950000000000; info@krega-onlinehandel.de; ; Birkenweg 31; Brakel; 33034; Allemagne