ASIC Design for a Coherent Optical Receiver DSPU: Design issues related to high-speed MOS ASIC for a coherent optical QPSK with polarization multiplex receiver DSPU - Couverture souple

Herath, Vijitha Rohana

 
9783844304190: ASIC Design for a Coherent Optical Receiver DSPU: Design issues related to high-speed MOS ASIC for a coherent optical QPSK with polarization multiplex receiver DSPU
Couverture souple
ISBN 10 : 3844304193 ISBN 13 : 9783844304190
Editeur : LAP LAMBERT Academic Publishing, 2011

Synopsis

The exponential growth of the internet traffic makes it necessary to increase the transmission capacity of the backbone optical transmission system. The coherent optical quadrature PSK (QPSK) with polarization multiplex quadruple channel capacity over the intensity modulation scheme. This upgrades existing 10 Gbit/s links to 40 Gbit/s. This book introduces you to the practicle implementation of the receiver DSPU ASIC of such a system. Chapter 1 introduces the design problem. Chapter 2 starts with an introduction to the optical synchronous QPSK transmission systems and discusses the carrier & data recovery algorithms. Chapter 2 concludes with an introduction to the DSPU ASIC architecture. Chapter 3 discusses the implementation of the DSPU ASIC. The chapter starts with an introduction to the 130 nm technology node and then discuss transmission line implementation issues, DSPU input interface design, and the full DSPU implementation. Finally, test results are presented. Chapter 4 introduces a novel clock skew estimation algorithm. This algorithm calculates the clock skew when process variations and nonuniform temparature varitions are present.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

The exponential growth of the internet traffic makes it necessary to increase the transmission capacity of the backbone optical transmission system. The coherent optical quadrature PSK (QPSK) with polarization multiplex quadruple channel capacity over the intensity modulation scheme. This upgrades existing 10 Gbit/s links to 40 Gbit/s. This book introduces you to the practicle implementation of the receiver DSPU ASIC of such a system. Chapter 1 introduces the design problem. Chapter 2 starts with an introduction to the optical synchronous QPSK transmission systems and discusses the carrier & data recovery algorithms. Chapter 2 concludes with an introduction to the DSPU ASIC architecture. Chapter 3 discusses the implementation of the DSPU ASIC. The chapter starts with an introduction to the 130 nm technology node and then discuss transmission line implementation issues, DSPU input interface design, and the full DSPU implementation. Finally, test results are presented. Chapter 4 introduces a novel clock skew estimation algorithm. This algorithm calculates the clock skew when process variations and nonuniform temparature varitions are present.

Biographie de l'auteur

Dr. Vijitha R. Herath received BS(EE)from the University of Peradeniya, Sri Lanka, MS(ECE) from the University of Miami, USA, and Dr. -Ing. (EE) from the University of Paderborn, Germany. He is a member of IEEE, OSA and IEEE MTT-S Sri Lanka chapter. He is attached to the Dept. of Electrical & Electronic Eng., University of Peradeniya.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2011
Langue
anglais
ISBN 10 
3844304193
ISBN 13 
9783844304190
Reliure
Broché
Nombre de pages
112
Coordonnées du fabricant
non disponible
Personne responsable
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