Layout-Aware Analog Synthesis Methodology: Approaches for Parasitic-Inclusive Symbolic Circuit Representation and Extraction for Synthesis - Couverture souple

Badaoui, Raoul

 
9783844304794: Layout-Aware Analog Synthesis Methodology: Approaches for Parasitic-Inclusive Symbolic Circuit Representation and Extraction for Synthesis
Couverture souple
ISBN 10 : 3844304797 ISBN 13 : 9783844304794
Editeur : LAP LAMBERT Academic Publishing, 2011

Synopsis

Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasite-inclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met; this is time consuming. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself. The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified unsized circuit; these structures are generated pre-synthesis and contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, their location and routing characteristics.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Layout-induced parasitics have significant effects on the behavior of circuits in general and the performance of high-frequency analog ones in particular. To achieve parasite-inclusive performance-closure, layout-aware circuit synthesis methodologies are beginning to emerge. In layout-in-the-loop synthesis methodologies, performance analysis is based on the generation of a concrete layout for the explored circuit sizes. A parasite-inclusive circuit is extracted from the layout using a standard extractor and is analyzed using a simulator to determine whether the required constraints are met; this is time consuming. Various approaches of estimating parasitics lack the correctness that would only come from examining the layout itself. The proposed approach tries to include the exactness of the layout to be generated without actually generating it. It relies on using pre-generated structures for the specified unsized circuit; these structures are generated pre-synthesis and contain the information that a layout would have provided to a synthesis process if it was to be generated. This information contains extraction specifics for modules, their location and routing characteristics.

Biographie de l'auteur

Raoul Badaoui holds a PhD in computer engineering from the University of Cincinnati and a bachelor of engineering from the American University of Beirut. His research focus was on Analog VLSI Electronic Design Automation. He currently works as a research and development engineering lead for Certify, an FPGA prototyping software at Synopsys.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2011
Langue
anglais
ISBN 10 
3844304797
ISBN 13 
9783844304794
Reliure
Broché
Nombre de pages
176
Coordonnées du fabricant
non disponible
Personne responsable
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