Fault-tolerant Cells for Nanoelectronic Computing: Designing the building blocks for reliable nanoelectronic systems using a hierarchical tolerant approach - Couverture souple

Martorell, Ferran

 
9783844319545: Fault-tolerant Cells for Nanoelectronic Computing: Designing the building blocks for reliable nanoelectronic systems using a hierarchical tolerant approach
Couverture souple
ISBN 10 : 3844319549 ISBN 13 : 9783844319545
Editeur : LAP LAMBERT Academic Publishing, 2011

Synopsis

New nanometric technologies hold the promise of device integration density increases of several orders of magnitude and, accordingly, an increase of system performance and functionality. However, this improved integration density comes at the cost of a dramatic reduction of several orders of magnitude on the device quality and, in general, on the operation reliability of circuits. The causes for this increased error rate are inherent to the device's dimensions. It is widely acknowledged that fault and defect tolerant strategies will be required in future nanoelectronic systems. This book analyzes the aggression sources causing the increased fault rates and how they affect the reliability of logic gate operation. From this analysis a new logic cell structure is designed and analyzed. The cell is proposed to be used as the building block for a hierarchical approach to fault-tolerant nanoelectronic architectures. This book will be especially useful for researchers and engineers working in the development of nanoelectronic systems.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

New nanometric technologies hold the promise of device integration density increases of several orders of magnitude and, accordingly, an increase of system performance and functionality. However, this improved integration density comes at the cost of a dramatic reduction of several orders of magnitude on the device quality and, in general, on the operation reliability of circuits. The causes for this increased error rate are inherent to the device's dimensions. It is widely acknowledged that fault and defect tolerant strategies will be required in future nanoelectronic systems. This book analyzes the aggression sources causing the increased fault rates and how they affect the reliability of logic gate operation. From this analysis a new logic cell structure is designed and analyzed. The cell is proposed to be used as the building block for a hierarchical approach to fault-tolerant nanoelectronic architectures. This book will be especially useful for researchers and engineers working in the development of nanoelectronic systems.

Biographie de l'auteur

F.Martorell is PhD in electronic engineering (Polytechnic University of Catalonia). He has a long experience in new technologies research from nanoelectronic technologies to asynchronous systems both at university and industry. Currently, he is an ASIC engineer in eSilicon Corporation.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2011
Langue
anglais
ISBN 10 
3844319549
ISBN 13 
9783844319545
Reliure
Broché
Nombre de pages
148
Coordonnées du fabricant
non disponible
Personne responsable
KreGa Onlinehandel GmbH
4950000000000
info@krega-onlinehandel.de

Birkenweg 31
Brakel
33034
Allemagne