An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs - Couverture souple

Anwer, Jahanzeb; Hisham Bin Hamid, Nor; Sagayan Asirvadam, Vijanth

 
9783844332636: An Improved Markov Random Field Design Approach For Digital Circuits: Introducing Fault-Tolerance With Higher Noise-Immunity For The Nano-Circuits As Compared To CMOS And MRF Designs
Couverture souple
ISBN 10 : 3844332634 ISBN 13 : 9783844332636
Editeur : LAP Lambert Academic Publishing, 2011

Synopsis

As the MOSFET dimensions scale down to nanoscale level, the reliability of circuits based on these devices decreases. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal noise sources to provide a more rigorous noise environment for the simulation of nanoscale circuits. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The re-designed MRF is termed as Improved-MRF. By simulating various test circuits in Cadence, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

À propos des auteurs

The authors work under the banner of fault-tolerance research group in Universiti Teknologi PETRONAS (UTP). The group is conducting research on various aspects of fault-tolerant circuit design with the support of UTP and MOSTI (Ministry of Science, Technology and Innovation) Malaysia.

The authors work under the banner of fault-tolerance research group in Universiti Teknologi PETRONAS (UTP). The group is conducting research on various aspects of fault-tolerant circuit design with the support of UTP and MOSTI (Ministry of Science, Technology and Innovation) Malaysia.

The authors work under the banner of fault-tolerance research group in Universiti Teknologi PETRONAS (UTP). The group is conducting research on various aspects of fault-tolerant circuit design with the support of UTP and MOSTI (Ministry of Science, Technology and Innovation) Malaysia.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP Lambert Academic Publishing
Date d'édition
2011
Langue
anglais
ISBN 10 
3844332634
ISBN 13 
9783844332636
Reliure
Broché
Nombre de pages
88
Coordonnées du fabricant
non disponible
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