Articles liés à Low Power Flash ADC: VLSI Technology

Low Power Flash ADC: VLSI Technology - Couverture souple

Subba Reddy, Murra

 
9783845440842: Low Power Flash ADC: VLSI Technology

Synopsis

In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.

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Présentation de l'éditeur

In this project, a new design for a low power CMOS flash Analog-to-Digital Converter (ADC) is proposed. A 6-bit flash ADC, with a maximum acquisition speed of 1 GHz, is implemented in a 1.2 V analog supply voltage. Microwind simulation results for the proposed flash ADC verifying the analytical results are also given. It shows that the proposed 6-bit flash ADC consumes about 72 mW in a commercial 90 nm CMOS process. The new design offers lower number of comparators and lower power consumption compared with the traditional flash ADC.

Biographie de l'auteur

It describes how to design a low power flash ADC which gives high speed,low cost&less complexity rather than conventional flash ADC.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.