Efficient Hardware Implementation of an Advanced Turbo Decoder: An ASIC Implementation - Couverture souple

Venkatesh, Naresh Kumar

 
9783847308553: Efficient Hardware Implementation of an Advanced Turbo Decoder: An ASIC Implementation
Couverture souple
ISBN 10 : 3847308556 ISBN 13 : 9783847308553
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

Turbo decoder is a key component of the emerging 3G mobile communication. The focus of this work is towards developing an application specific integrated circuit for an advanced turbo decoder. The methodology starts from RTL models which can be used for software solution and proceeds towards hardware implementation. In the current project work, Turbo encoder and turbo decoder with SOVA and log-MAP decoding algorithms were modelled from algorithmic level, concentrating on the functional correctness rather than on implementation architecture. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleaver in the presence of additive white Gaussian noise, using MATLAB. The hardware of the Turbo decoder has been modelled in VHDL, simulated in VCS, synthesized using Design compiler and physical implementation has been carried out using IC Compiler.

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Présentation de l'éditeur

Turbo decoder is a key component of the emerging 3G mobile communication. The focus of this work is towards developing an application specific integrated circuit for an advanced turbo decoder. The methodology starts from RTL models which can be used for software solution and proceeds towards hardware implementation. In the current project work, Turbo encoder and turbo decoder with SOVA and log-MAP decoding algorithms were modelled from algorithmic level, concentrating on the functional correctness rather than on implementation architecture. The effect on performance due to variation in parameters like frame length, number of iterations, type of encoding scheme and type of the interleaver in the presence of additive white Gaussian noise, using MATLAB. The hardware of the Turbo decoder has been modelled in VHDL, simulated in VCS, synthesized using Design compiler and physical implementation has been carried out using IC Compiler.

Biographie de l'auteur

I have completed M.Sc [Engineering] VLSI System Design at M.S. Ramaiah School of Advanced Studies, Bangalore.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
3847308556
ISBN 13 
9783847308553
Reliure
Broché
Nombre de pages
96
Coordonnées du fabricant
non disponible
Personne responsable
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