Low Power and High Performance Array Multiplier: Design and Analysis - Couverture souple

Sharma, Tripti; Sharma, K. G.; Singh, B. P.

 
9783847310310: Low Power and High Performance Array Multiplier: Design and Analysis
Couverture souple
ISBN 10 : 3847310313 ISBN 13 : 9783847310310
Editeur : LAP LAMBERT Academic Publishing, 2011

Synopsis

Arithmetic circuits, like adders and multipliers, are one of the basic components in the design of communication circuits. In fact 8.72% of all instructions in a typical scientific program are multiplies. The multiplier is a fairly large block of a computing system. Multiplier is not only a high-delay block but also a significant source of power dissipation. That’s why, if one also aims to minimize power consumption, it is of great interest to identify the techniques to be applied to reduce delay by using various delay optimizations. Array architecture is a popular technique to implement the multipliers due to its compact structure. In this book, six array multiplier circuits using different AND cells and XOR gates have been designed, simulated, analyzed and compared. This analysis should help shed some light on the low power and high throughput 2×2 array multiplier cells and should be especially useful for post graduate students and research scholars working in low power VLSI circuit design field.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Arithmetic circuits, like adders and multipliers, are one of the basic components in the design of communication circuits. In fact 8.72% of all instructions in a typical scientific program are multiplies. The multiplier is a fairly large block of a computing system. Multiplier is not only a high-delay block but also a significant source of power dissipation. That’s why, if one also aims to minimize power consumption, it is of great interest to identify the techniques to be applied to reduce delay by using various delay optimizations. Array architecture is a popular technique to implement the multipliers due to its compact structure. In this book, six array multiplier circuits using different AND cells and XOR gates have been designed, simulated, analyzed and compared. This analysis should help shed some light on the low power and high throughput 2×2 array multiplier cells and should be especially useful for post graduate students and research scholars working in low power VLSI circuit design field.

Biographie de l'auteur

Tripti Sharma, M.Tech., Ph.D. (pursuing): Achieved M.Tech.(VLSI Design) degree from MITS (Deemed University), Pursuing Ph.D. from Gyan Vihar University, Jaipur, Currently working as an Assistant Professor at MITS (Deemed University), Lakshmangarh, INDIA.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2011
Langue
anglais
ISBN 10 
3847310313
ISBN 13 
9783847310310
Reliure
Broché
Nombre de pages
68
Coordonnées du fabricant
non disponible
Personne responsable
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