Power and Thermal Management in Multicores: Preparing microprocessors for the Dark Silicon era - Couverture souple

Cebrián, Juan M.; L. Aragón, Juan; Kaxiras, Stefanos

 
9783848434565: Power and Thermal Management in Multicores: Preparing microprocessors for the Dark Silicon era
Couverture souple
ISBN 10 : 3848434563 ISBN 13 : 9783848434565
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

Thermal and power related issues are common in most modern microprocessors. We are not only talking about servers, but also mobile devices, desktop computers, laptop, GPUs, APUs, etc. For many years microprocessor design has been (and is) limited by power dissipation and temperature. Many studies refer to these key factors as the "Power Wall". Even today, this "Power Wall" is still limiting the number of cores that can be placed on the same die. In this project we worked in the design, implementation and testing of microarchitecture techniques for accurately adapting the processor performance to power constraints in the single core scenario, multi-core scenario and 3D die-stacked core scenario. We first introduce "Power-Tokens", to approximate the power being consumed by the processor in real time. Later we will discuss different mechanisms based on pipeline throttling, confidence estimation, instruction criticality information, to adapt the processor to a predefined power budget.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Thermal and power related issues are common in most modern microprocessors. We are not only talking about servers, but also mobile devices, desktop computers, laptop, GPUs, APUs, etc. For many years microprocessor design has been (and is) limited by power dissipation and temperature. Many studies refer to these key factors as the "Power Wall". Even today, this "Power Wall" is still limiting the number of cores that can be placed on the same die. In this project we worked in the design, implementation and testing of microarchitecture techniques for accurately adapting the processor performance to power constraints in the single core scenario, multi-core scenario and 3D die-stacked core scenario. We first introduce "Power-Tokens", to approximate the power being consumed by the processor in real time. Later we will discuss different mechanisms based on pipeline throttling, confidence estimation, instruction criticality information, to adapt the processor to a predefined power budget.

Biographie de l'auteur

Juan Manuel Cebrián (right) was born in Albacete, Spain, in 1982. Got his B.Sc in Computer Engineering on July 2006, M.Sc in July 2007 and finished his Ph.D on September 2011 (University of Murcia) with the qualification of Summa Cum Laude. His research interests lay in the field of Computer Architecture, particularly in energy efficient designs.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
3848434563
ISBN 13 
9783848434565
Reliure
Broché
Nombre de pages
188
Coordonnées du fabricant
non disponible
Personne responsable
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