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Design of CMOS Low Power Folding and Interpolating ADC: Optimization of Area and Power for Medium Resolution Applications - Couverture souple

Oza, Shruti; Devashrayee, Niranjan

 
9783848480180: Design of CMOS Low Power Folding and Interpolating ADC: Optimization of Area and Power for Medium Resolution Applications
Couverture souple
ISBN 10 : 3848480182 ISBN 13 : 9783848480180
Editeur : LAP LAMBERT Academic Publishing, 2012

Synopsis

Folding and Interpolating ADCs have been shown to be an effective means of digitization of high bandwidth signals at intermediate resolution. The book focuses on design of low power Folding and Interpolating ADC using novel cascaded folding amplifier. The architecture improvements and optimization of various sub blocks are discussed in the book. The pre- processing block-folding amplifier is designed to reduce power consumption and settling time. In ADC, comparators consume the major part of the total power. The converter architecture is designed with reduced number of comparators and minimum hardware. For further reduction of latency and number of comparators, folding amplifier is used in the design of coarse and fine converter both. To reduce the power consumption, encoder based on XOR-OR logic is used. The design is implemented using 0.35um technology at 3.3V.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

Folding and Interpolating ADCs have been shown to be an effective means of digitization of high bandwidth signals at intermediate resolution. The book focuses on design of low power Folding and Interpolating ADC using novel cascaded folding amplifier. The architecture improvements and optimization of various sub blocks are discussed in the book. The pre- processing block-folding amplifier is designed to reduce power consumption and settling time. In ADC, comparators consume the major part of the total power. The converter architecture is designed with reduced number of comparators and minimum hardware. For further reduction of latency and number of comparators, folding amplifier is used in the design of coarse and fine converter both. To reduce the power consumption, encoder based on XOR-OR logic is used. The design is implemented using 0.35um technology at 3.3V.

Biographie de l'auteur

Dr. Shruti Oza is presently working as a head and associate professor at Kalol Institute of Technology & Research Centre. She did M.Tech. and Ph.D. from Nirma University. She has published/ presented more than 40 research papers in various international/ national journals/conferences. Her area of interests is analog/mixed mode VLSI design.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2012
Langue
anglais
ISBN 10 
3848480182
ISBN 13 
9783848480180
Reliure
Broché
Nombre de pages
196
Coordonnées du fabricant
non disponible
Personne responsable
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