Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks - Couverture souple

Name: Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks
Author: Brunschwiler, Thomas
ISBN: 9783954040346

Brunschwiler, Thomas

9783954040346: Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks

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ISBN 10 : 3954040344 ISBN 13 : 9783954040346

Editeur : Cuvillier, 2012

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�diteur: Cuvillier
Date d'�dition: 2012
Langue: anglais
ISBN 10: 3954040344
ISBN 13: 9783954040346
Reliure: Broch�
Nombre de pages: 172
Coordonn�es du fabricant: info@cuvillier.de
info@cuvillier.de

Nonnenstieg 8
G�ttingen
37075
Allemagne

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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks

Brunschwiler, Thomas

Edit� par Cuvillier, 2012

ISBN 10 : 3954040344 ISBN 13 : 9783954040346

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PAP. Etat : New. New Book. Shipped from UK. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. N� de r�f. du vendeur L0-9783954040346

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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks

Brunschwiler, Thomas

Edit� par Cuvillier, 2012

ISBN 10 : 3954040344 ISBN 13 : 9783954040346

Neuf PAP

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PAP. Etat : New. New Book. Delivered from our UK warehouse in 4 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. N� de r�f. du vendeur L0-9783954040346

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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks

Brunschwiler, Thomas

Edit� par Cuvillier, 2012

ISBN 10 : 3954040344 ISBN 13 : 9783954040346

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Etat : New. N� de r�f. du vendeur I-9783954040346

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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks

Thomas Brunschwiler

Edit� par Cuvillier Apr 2012, 2012

ISBN 10 : 3954040344 ISBN 13 : 9783954040346

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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Vertical integration of integrated circuit dies offers tremendous opportunities from an architectural as well as from an economical standpoint. Memory proximity supports performance scaling, and might enable significant energy savings. Partitioning of the corresponding functionalities and technologies into individual tiers can improve yield and modularity substantially.The paradigm change of stacking active components has a direct impact on heat-removal concepts and is therefore the motivation of this thesis. A stack comprised of a single logic layer in combination with multiple memory dies was identified as the limit for traditional back-side heat removal. To minimize junction temperatures, a stacking sequence with the high heat-flux component in close proximity to the cold plate is proposed.Interlayer cooling is the only volumetric heat-removal solution that scales with the number of dies in the stack. Hence, the focus of this thesis has been to identify the potential of interlayer cooling and to provide a modeling framework. Fundamental heat-transfer building blocks, such as unit-cell geometries, fluid structure modulation, fluid focusing, as well as four-port fluid delivery supporting power-map-aware heat removal, are discussed. Moreover, the theoretical foundation was experimentally validated on resistively heated convective test cavities. Therefore, specific bonding and insulation schemes were developed. Finally, the interlayer cooling performance was demonstrated on a pyramid chip stack. 172 pp. Englisch. N� de r�f. du vendeur 9783954040346

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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks

Thomas Brunschwiler

Edit� par Cuvillier, 2012

ISBN 10 : 3954040344 ISBN 13 : 9783954040346

Neuf Taschenbuch

impression � la demande

Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne

�valuation du vendeur 5 sur 5 �toiles

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Vertical integration of integrated circuit dies offers tremendous opportunities from an architectural as well as from an economical standpoint. Memory proximity supports performance scaling, and might enable significant energy savings. Partitioning of the corresponding functionalities and technologies into individual tiers can improve yield and modularity substantially.The paradigm change of stacking active components has a direct impact on heat-removal concepts and is therefore the motivation of this thesis. A stack comprised of a single logic layer in combination with multiple memory dies was identified as the limit for traditional back-side heat removal. To minimize junction temperatures, a stacking sequence with the high heat-flux component in close proximity to the cold plate is proposed.Interlayer cooling is the only volumetric heat-removal solution that scales with the number of dies in the stack. Hence, the focus of this thesis has been to identify the potential of interlayer cooling and to provide a modeling framework. Fundamental heat-transfer building blocks, such as unit-cell geometries, fluid structure modulation, fluid focusing, as well as four-port fluid delivery supporting power-map-aware heat removal, are discussed. Moreover, the theoretical foundation was experimentally validated on resistively heated convective test cavities. Therefore, specific bonding and insulation schemes were developed. Finally, the interlayer cooling performance was demonstrated on a pyramid chip stack. N� de r�f. du vendeur 9783954040346

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Interlayer Thermal Management of High-Performance Microprocessor Chip Stacks

Brunschwiler, Thomas

Edit� par Jentzsch-Cuvillier, Annette, 2012

ISBN 10 : 3954040344 ISBN 13 : 9783954040346

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Vendeur : moluna, Greven, Allemagne

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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. KlappentextrnrnVertical integration of integrated circuit dies offers tremendous opportunities from an architectural as well as from an economical standpoint. Memory proximity supports performance scaling, and might enable significant energy sav. N� de r�f. du vendeur 119168031

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