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Design closure: Integrated circuit, Static timing analysis, Placement (EDA), Routing (electronic design automation), Moore's law, Signal integrity, Logic synthesis - Couverture souple

 
9786134223188: Design closure: Integrated circuit, Static timing analysis, Placement (EDA), Routing (electronic design automation), Moore's law, Signal integrity, Logic synthesis

Synopsis

Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. Design closure is the process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and objectives. Every step in the IC design (such as static timing analysis, placement, routing, and so on) is already complex and often forms its own field of study. This article, however, looks at the overall design closure process, which takes a chip from its initial design state to the final form in which all of its design constraints are met.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Reseña del editor

Please note that the content of this book primarily consists of articles available from Wikipedia or other free sources online. Design closure is the process by which a VLSI design is modified from its initial description to meet a growing list of design constraints and objectives. Every step in the IC design (such as static timing analysis, placement, routing, and so on) is already complex and often forms its own field of study. This article, however, looks at the overall design closure process, which takes a chip from its initial design state to the final form in which all of its design constraints are met.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.