Energy Efficient and Fault-tolerant Computing - Couverture souple

Natarajan, Jayaram

9786138916208: Energy Efficient and Fault-tolerant Computing

Couverture souple

ISBN 10 : 6138916204 ISBN 13 : 9786138916208

Editeur : Scholars' Press, 2019

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L'un des d�fis rencontr�s aujourd'hui dans la conception des microprocesseurs est d'obtenir l'efficacit� �nerg�tique, la vitesse et la fiabilit� en m�me temps avec la mise � l'�chelle de la technologie, face aux variations extr�mes des processus. La variation du comportement de retard de la m�me conception � l'int�rieur de la matrice et du die-to-die augmente consid�rablement aux nœuds technologiques inf�rieurs � 10 nm. En outre, les variations de synchronisation pendant le fonctionnement de la puce se produisent en raison de facteurs dynamiques tels que la charge de travail, la temp�rature, le vieillissement. Pour garantir l'exactitude op�rationnelle � vie dans les incertitudes de synchronisation, des marges de s�curit� sous la forme de bandes de protection ponctuelles sont incorpor�es dans la conception, ce qui entra�ne des inefficacit�s de vitesse �nerg�tique. Ce livre fait une enqu�te litt�raire sur la conception num�rique et les techniques micro-architecturales dans la litt�rature pour relever les d�fis ci-dessus. Deux m�thodes sont d�crites en d�tail (1) Une m�thodologie d'auto-test et de r�glage de la vitesse de post-fabrication � faible co�t pour une couverture de vitesse de recharge et trouver la fr�quence d'horloge maximale fiable de chaque pipeline de processeur dans un syst�me multiprocesseur. (2) Conception et fonctionnement d'une nouvelle conception de pipeline tol�rante � la variation de synchronisation, ce qui �limine le besoin d'incorporer des marges de s�curit� de synchronisation.

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�diteur: Scholars' Press
Date d'�dition: 2019
Langue: anglais
ISBN 10: 6138916204
ISBN 13: 9786138916208
Reliure: Broch�
Nombre de pages: 136
Coordonn�es du fabricant: non disponible
Personne responsable: non disponible

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Energy Efficient and Fault-tolerant Computing

Jayaram Natarajan

Edit� par Scholars' Press Okt 2019, 2019

ISBN 10 : 6138916204 ISBN 13 : 9786138916208

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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins. 136 pp. Englisch. N� de r�f. du vendeur 9786138916208

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Energy Efficient and Fault-tolerant Computing

Jayaram Natarajan

Edit� par Scholars\' Press, 2019

ISBN 10 : 6138916204 ISBN 13 : 9786138916208

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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Natarajan JayaramJayaram Natarajan was born in Mumbai, India and received his BS in Electronics Engineering from University of Mumbai, MS and PhD in Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta. H. N� de r�f. du vendeur 335816032

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Energy Efficient and Fault-tolerant Computing

Jayaram Natarajan

Edit� par Scholars' Press Okt 2019, 2019

ISBN 10 : 6138916204 ISBN 13 : 9786138916208

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Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne

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Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins.VDM Verlag, Dudweiler Landstra�e 99, 66123 Saarbr�cken 136 pp. Englisch. N� de r�f. du vendeur 9786138916208

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Energy Efficient and Fault-tolerant Computing : A comprehensive manual on hardware and micro-architecture techniques for fault-tolerance, low power and high performance

Jayaram Natarajan

Edit� par Scholars' Press, 2019

ISBN 10 : 6138916204 ISBN 13 : 9786138916208

Neuf Taschenbuch

impression � la demande

Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne

�valuation du vendeur 5 sur 5 �toiles

Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - One of the challenges faced today in the design of microprocessors is to obtain energy efficiency, speed and reliability at the same time with technology scaling, in the face of extreme process variations. The variation in delay behavior of the same design within-die and die-to-die increases significantly at technology nodes below 10nm. In addition, timing variations during chip operation occur due to dynamically changing factors like workload, temperature, aging. To guarantee lifetime operational correctness under timing uncertainties, safety margins in the form of one-time worst-case guard-bands are incorporated into the design resulting in energy-speed inefficiencies. This book does literature survey of the digital design and micro-architectural techniques in literature to tackle the above challenges. Two methods are described in detail (1) A low cost post-manufacturing self-testing and speed-tuning methodology to top-up speed coverage and find the maximum reliable clock frequency of each processor pipeline in a multi-processor system (2) Design and operation of a novel timing variation tolerant pipeline design, which eliminates the need to incorporate timing safety margins. N� de r�f. du vendeur 9786138916208

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