Articles liés à Time-to-Digital Converter dedicated to Dividerless...

Time-to-Digital Converter dedicated to Dividerless ADPLL applications: Design challenges, method and implementation - Couverture souple

Saad, Sehmi; Ben Hammadi, Aymen

 
9786139902491: Time-to-Digital Converter dedicated to Dividerless ADPLL applications: Design challenges, method and implementation
Couverture souple
ISBN 10 : 6139902495 ISBN 13 : 9786139902491
Editeur : LAP LAMBERT Academic Publishing, 2018

Synopsis

The book presents a novel Time-to-Digital Converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a Gated Ring Oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. Contents: 1) An Enhanced Variable Phase Accumulator with Minimal Hardware Complexity Dedicated to ADPLL Applications. 2) A 15b, Sub-10ps resolution, Gateable Pseudo-Delay Ring Oscillator Time-to-Digital Converter for wide range RF Applications. 3) A new hybrid TDC based on GRO-Pseudo Delay architecture with fractional code and wide time range detection for divider-less ADPLL. Complete list of Authors: Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi and Kamel Besbes.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

The book presents a novel Time-to-Digital Converter (TDC) for All Digital Phase Locked Loop (ADPLL) able to reach high linearity and wide input range with normalized fractional output code. The topology is based on startable Pseudo differential delay cells. It arbiters in a Gated Ring Oscillator (GRO) format in manner to extend measurement time interval. A normalization unit is developed to free calibrate output and to measure phase errors for divider-less ADPLL applications. Contents: 1) An Enhanced Variable Phase Accumulator with Minimal Hardware Complexity Dedicated to ADPLL Applications. 2) A 15b, Sub-10ps resolution, Gateable Pseudo-Delay Ring Oscillator Time-to-Digital Converter for wide range RF Applications. 3) A new hybrid TDC based on GRO-Pseudo Delay architecture with fractional code and wide time range detection for divider-less ADPLL. Complete list of Authors: Sehmi Saad, Mongia Mhiri, Aymen Ben Hammadi and Kamel Besbes.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2018
Langue
anglais
ISBN 10 
6139902495
ISBN 13 
9786139902491
Reliure
Broché
Nombre de pages
60
Coordonnées du fabricant
non disponible
Personne responsable
KreGa Onlinehandel GmbH
4950000000000
info@krega-onlinehandel.de

Birkenweg 31
Brakel
33034
Allemagne