Articles liés à Design of High Speed and Low Power Configurable Booth...
Synopsis
A configurable multiplier optimized for low power and high speed operations and which can be configured either for single 16-bit multiplication operation, single 8-bit multiplication or twin parallel 8-bit multiplication is designed. The output product can be truncated to further decrease Power consumption and increase speed by sacrificing a bit of output precision. Furthermore, the proposed multiplier maintains an acceptable output quality with enough accuracy when truncation is performed. Thus it provides a flexible arithmetic capacity and a trade off between output precision and power consumption. The approach also dynamically detects the input range of multipliers and disables the switching operation of the non-effective ranges. Thus the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing the speed of operation.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Résultats de recherche pour Design of High Speed and Low Power Configurable Booth...
Image fournie par le vendeur
Design of High Speed and Low Power Configurable Booth Multiplier
Edité par
LAP LAMBERT Academic Publishing Aug 2021, 2021
ISBN 10 : 6204197657
ISBN 13 : 9786204197654
Neuf
Taschenbuch
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -A configurable multiplier optimized for low power and high speed operations and which can be configured either for single 16-bit multiplication operation, single 8-bit multiplication or twin parallel 8-bit multiplication is designed. The output product can be truncated to further decrease Power consumption and increase speed by sacrificing a bit of output precision. Furthermore, the proposed multiplier maintains an acceptable output quality with enough accuracy when truncation is performed. Thus it provides a flexible arithmetic capacity and a trade off between output precision and power consumption. The approach also dynamically detects the input range of multipliers and disables the switching operation of the non-effective ranges. Thus the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing the speed of operation. 88 pp. Englisch. N° de réf. du vendeur 9786204197654
Acheter neuf
EUR 54,90
Expédition à EUR 23
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
Design of High Speed and Low Power Configurable Booth Multiplier
Edité par
LAP LAMBERT Academic Publishing, 2021
ISBN 10 : 6204197657
ISBN 13 : 9786204197654
Neuf
Couverture souple
Vendeur : moluna, Greven, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Shashidhar K.K. Shashidhar having more than 20 years of experience in the field of teaching. Completed Ph.D from GITAM University. M.Tech in VLSI System Design from JNTUH. At present working as Associate professor in the department o. N° de réf. du vendeur 506238143
Acheter neuf
EUR 45,45
Expédition à EUR 48,99
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
Design of High Speed and Low Power Configurable Booth Multiplier
Edité par
LAP LAMBERT Academic Publishing Aug 2021, 2021
ISBN 10 : 6204197657
ISBN 13 : 9786204197654
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -A configurable multiplier optimized for low power and high speed operations and which can be configured either for single 16-bit multiplication operation, single 8-bit multiplication or twin parallel 8-bit multiplication is designed. The output product can be truncated to further decrease Power consumption and increase speed by sacrificing a bit of output precision. Furthermore, the proposed multiplier maintains an acceptable output quality with enough accuracy when truncation is performed. Thus it provides a flexible arithmetic capacity and a trade off between output precision and power consumption. The approach also dynamically detects the input range of multipliers and disables the switching operation of the non-effective ranges. Thus the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing the speed of operation.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 88 pp. Englisch. N° de réf. du vendeur 9786204197654
Acheter neuf
EUR 54,90
Expédition à EUR 60
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Design of High Speed and Low Power Configurable Booth Multiplier
Edité par
LAP LAMBERT Academic Publishing, 2021
ISBN 10 : 6204197657
ISBN 13 : 9786204197654
Neuf
Taschenbuch
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - A configurable multiplier optimized for low power and high speed operations and which can be configured either for single 16-bit multiplication operation, single 8-bit multiplication or twin parallel 8-bit multiplication is designed. The output product can be truncated to further decrease Power consumption and increase speed by sacrificing a bit of output precision. Furthermore, the proposed multiplier maintains an acceptable output quality with enough accuracy when truncation is performed. Thus it provides a flexible arithmetic capacity and a trade off between output precision and power consumption. The approach also dynamically detects the input range of multipliers and disables the switching operation of the non-effective ranges. Thus the ineffective circuitry can be efficiently deactivated, thereby reducing power consumption and increasing the speed of operation. N° de réf. du vendeur 9786204197654
Acheter neuf
EUR 55,56
Expédition à EUR 60,75
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
Design of High Speed and Low Power Configurable Booth Multiplier
Edité par
LAP LAMBERT Academic Publishing, 2021
ISBN 10 : 6204197657
ISBN 13 : 9786204197654
Neuf
Taschenbuch
Vendeur : preigu, Osnabrück, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. Design of High Speed and Low Power Configurable Booth Multiplier | K. Shashidhar | Taschenbuch | Englisch | 2021 | LAP LAMBERT Academic Publishing | EAN 9786204197654 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. N° de réf. du vendeur 120521188
Acheter neuf
EUR 47,90
Expédition à EUR 70
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : 5 disponible(s)