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Synopsis
This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins.
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Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis
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Quantum Key Distribution Using FPGA
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Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis
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Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Autor/Autorin: Jumaa Noor KareemNoor Kareem Jumaa was received her B.Sc degree in computer engineering from university of Baghdad, Iraq in 2010 and the M.Sc degree in quantum cryptography and data security from the department of electronics and com. N° de réf. du vendeur 548987925
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Quantum Key Distribution Using FPGA
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Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis
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Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis
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Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis
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Noor Publishing Dez 2021, 2021
ISBN 10 : 6204720066
ISBN 13 : 9786204720067
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Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins. 100 pp. Englisch. N° de réf. du vendeur 9786204720067
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Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis (Paperback or Softback)
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ISBN 10 : 6204720066
ISBN 13 : 9786204720067
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Paperback or Softback. Etat : New. Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis 0.35. Book. N° de réf. du vendeur BBS-9786204720067
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Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis
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Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins. N° de réf. du vendeur 9786204720067
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Quantum Key Distribution Using FPGA: A Real Time Prototype, Design, and Analysis
Edité par
Noor Publishing Dez 2021, 2021
ISBN 10 : 6204720066
ISBN 13 : 9786204720067
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. Neuware -This book presents a study and analysis to investigate of a secret-key sharing in quantum technique and try to increase the key length and security level in the sifting key stage. Enhancements in sifting key stage and error correction stage are done by repeating the QKD protocol and encoding the key bits before sending them by adding a C_QUBITS technique. After that, 60% base probability is used to increase the protocol gain. The prototype is implemented with the default FPGA clock period which is 20 ns; the performance analysis shows a good enhancement in the speed of generation which is less than 20 ns and the number of used hardware pins is just 3 pins.Books on Demand GmbH, Überseering 33, 22297 Hamburg 100 pp. Englisch. N° de réf. du vendeur 9786204720067
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