OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC: VLSI PHYSICAL DESIGN - Couverture souple
Synopsis
Very Large Scale Integration (VLSI) is a process of creating an integrated circuit by linking a large number of transistors into a single chip. A 3D IC provides a positive effect on both execution and wirelength in a power system. A three dimensional integrated circuit would become a developing process where connection delays and power get reduced. The several layers of 3D IC which have been linked could be performed by utilizing through silicon via method. It offers better performance than the conventional approach due to decreased length and power consumption. A test access mechanism technique has become significant owing to the impact of sinking routing cost. If a large number of TSV has been employed, then it leads to superior area consumption and increases ultimate chip cost. Uneven distribution of TSV is occurred owing to the bonding stratum procedure. It affects not only the area but also wirelength and temperature. At the routing phase, through silicon via could be done by identifying whitespace from integrated circuit system.
Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.
Résultats de recherche pour OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR...
Image fournie par le vendeur
OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC
Edité par
LAP LAMBERT Academic Publishing Jan 2022, 2022
ISBN 10 : 6204741314
ISBN 13 : 9786204741314
Neuf
Taschenbuch
Vendeur : BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Very Large Scale Integration (VLSI) is a process of creating an integrated circuit by linking a large number of transistors into a single chip. A 3D IC provides a positive effect on both execution and wirelength in a power system. A three dimensional integrated circuit would become a developing process where connection delays and power get reduced. The several layers of 3D IC which have been linked could be performed by utilizing through silicon via method. It offers better performance than the conventional approach due to decreased length and power consumption. A test access mechanism technique has become significant owing to the impact of sinking routing cost. If a large number of TSV has been employed, then it leads to superior area consumption and increases ultimate chip cost. Uneven distribution of TSV is occurred owing to the bonding stratum procedure. It affects not only the area but also wirelength and temperature. At the routing phase, through silicon via could be done by identifying whitespace from integrated circuit system. 188 pp. Englisch. N° de réf. du vendeur 9786204741314
Acheter neuf
EUR 79,90
Expédition à EUR 23
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : 2 disponible(s)
Image fournie par le vendeur
OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC
Edité par
LAP Lambert Academic Publishing, 2022
ISBN 10 : 6204741314
ISBN 13 : 9786204741314
Neuf
Kartoniert / Broschiert
Vendeur : moluna, Greven, Allemagne
Évaluation du vendeur 4 sur 5 étoiles
Kartoniert / Broschiert. Etat : New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Very Large Scale Integration (VLSI) is a process of creating an integrated circuit by linking a large number of transistors into a single chip. A 3D IC provides a positive effect on both execution and wirelength in a power system. A three dimensional integr. N° de réf. du vendeur 567324681
Acheter neuf
EUR 64,09
Expédition à EUR 48,99
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : Plus de 20 disponibles
Image fournie par le vendeur
OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC | VLSI PHYSICAL DESIGN
Edité par
LAP LAMBERT Academic Publishing, 2022
ISBN 10 : 6204741314
ISBN 13 : 9786204741314
Neuf
Taschenbuch
Vendeur : preigu, Osnabrück, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC | VLSI PHYSICAL DESIGN | Pandiaraj K | Taschenbuch | Englisch | 2022 | LAP LAMBERT Academic Publishing | EAN 9786204741314 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu. N° de réf. du vendeur 121292738
Acheter neuf
EUR 67,10
Expédition à EUR 70
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : 5 disponible(s)
Image fournie par le vendeur
OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC
Edité par
LAP LAMBERT Academic Publishing Jan 2022, 2022
ISBN 10 : 6204741314
ISBN 13 : 9786204741314
Neuf
Taschenbuch
Vendeur : buchversandmimpf2000, Emtmannsberg, BAYE, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. This item is printed on demand - Print on Demand Titel. Neuware -Very Large Scale Integration (VLSI) is a process of creating an integrated circuit by linking a large number of transistors into a single chip. A 3D IC provides a positive effect on both execution and wirelength in a power system. A three dimensional integrated circuit would become a developing process where connection delays and power get reduced. The several layers of 3D IC which have been linked could be performed by utilizing through silicon via method. It offers better performance than the conventional approach due to decreased length and power consumption. A test access mechanism technique has become significant owing to the impact of sinking routing cost. If a large number of TSV has been employed, then it leads to superior area consumption and increases ultimate chip cost. Uneven distribution of TSV is occurred owing to the bonding stratum procedure. It affects not only the area but also wirelength and temperature. At the routing phase, through silicon via could be done by identifying whitespace from integrated circuit system.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 188 pp. Englisch. N° de réf. du vendeur 9786204741314
Acheter neuf
EUR 79,90
Expédition à EUR 60
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : 1 disponible(s)
Image fournie par le vendeur
OPTIMIZATION OF THERMAL AWARE MULTILEVEL ROUTING FOR 3D IC : VLSI PHYSICAL DESIGN
Edité par
LAP LAMBERT Academic Publishing, 2022
ISBN 10 : 6204741314
ISBN 13 : 9786204741314
Neuf
Taschenbuch
Vendeur : AHA-BUCH GmbH, Einbeck, Allemagne
Évaluation du vendeur 5 sur 5 étoiles
Taschenbuch. Etat : Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Very Large Scale Integration (VLSI) is a process of creating an integrated circuit by linking a large number of transistors into a single chip. A 3D IC provides a positive effect on both execution and wirelength in a power system. A three dimensional integrated circuit would become a developing process where connection delays and power get reduced. The several layers of 3D IC which have been linked could be performed by utilizing through silicon via method. It offers better performance than the conventional approach due to decreased length and power consumption. A test access mechanism technique has become significant owing to the impact of sinking routing cost. If a large number of TSV has been employed, then it leads to superior area consumption and increases ultimate chip cost. Uneven distribution of TSV is occurred owing to the bonding stratum procedure. It affects not only the area but also wirelength and temperature. At the routing phase, through silicon via could be done by identifying whitespace from integrated circuit system. N° de réf. du vendeur 9786204741314
Acheter neuf
EUR 80,86
Expédition à EUR 61,49
Expédition depuis Allemagne vers Etats-Unis
Expédition depuis Allemagne vers Etats-Unis
Quantité disponible : 1 disponible(s)