Low Leakage SRAM Memory: Design of Low Power High Performance SRAMMemory using Gate Leakage ReductionTechnique - Couverture souple

Mukherjee, Debasis

 
9786205517116: Low Leakage SRAM Memory: Design of Low Power High Performance SRAMMemory using Gate Leakage ReductionTechnique
Couverture souple
ISBN 10 : 6205517116 ISBN 13 : 9786205517116
Editeur : LAP LAMBERT Academic Publishing, 2022

Synopsis

I present some techniques to decrease the gate and other leakage dissipation in Deep Sub-Micron SRAM memories. This book reviews detail SRAM operations. This book also reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Finally, the book explores different circuit techniques to reduce the leakage power consumption. The W/L ratios are calculated from the equations of current in transistors (Linear and Saturation mode) for smooth read-write operation of both 0 and 1. I use W1/W3 = 1.5 and W4/W6 = 1.5. I first designed conventional SRAM memory and observed leakage current in various technology. In 90 nm technology conventional SRAM shows a leakage current of 1.87nA at steady state. Data retention gated-ground cache (DGR-cache) method reduces the leakage current to 100pA. Drowsy cache method reduces the leakage current to 84pA.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2022
Langue
anglais
ISBN 10 
6205517116
ISBN 13 
9786205517116
Reliure
Broché
Nombre de pages
68
Coordonnées du fabricant
non disponible
Personne responsable
KreGa Onlinehandel GmbH
4950000000000
info@krega-onlinehandel.de

Birkenweg 31
Brakel
33034
Allemagne