Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems - Couverture souple

Rajesh, B. Babu; Someswar, Prof. Dr. G. Manoj; Krishnanaik, Dr. V.

 
9786207460427: Design of Power Reduction in Very Large Scale Integrated Systems: Power Reduction In VLSI Systems
Couverture souple
ISBN 10 : 6207460421 ISBN 13 : 9786207460427
Editeur : LAP LAMBERT Academic Publishing, 2024

Synopsis

Testing low power very large scale integrated (VLSI) circuits in the recent times has become a critical problem area due to yield and reliability problems. This research work lays emphasis on reducing power dissipation during test application at logic level and register-transfer level (RTL) of abstraction of the VLSI design flow. In the initial stage, this research work addresses power reduction techniques in scan sequential circuits at the logic level of abstraction. Implementation of a new best primary input change (BPIC) technique based on a novel test application strategy has been proposed. The technique increases the correlation between successive states during shifting in test vectors and shifting out test responses by changing the primary inputs such that the smallest number of transitions is achieved. The new technique is test set dependent and it is applicable to small to medium sized full and partial scan sequential circuits.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Éditeur
LAP LAMBERT Academic Publishing
Date d'édition
2024
Langue
anglais
ISBN 10 
6207460421
ISBN 13 
9786207460427
Reliure
Broché
Nombre de pages
296
Coordonnées du fabricant
non disponible
Personne responsable
KreGa Onlinehandel GmbH
4950000000000
info@krega-onlinehandel.de

Birkenweg 31
Brakel
33034
Allemagne