Synopsis
Paperback. Pub Date: 2009 Pages: 239 Language: English Publisher: People's Posts and Telecommunications Press high speed CMOS circuit design Logical Effirt (English) is about how to get high-speed CMOS circuits. which is the high-speed integrated circuit designers eager to get technical. In the design. we are often faced with countless choices. high-speed CMOS circuits the Design Logical Effirt method (English version) will tell us how these choices easier and more skills. The high-speed CMOS circuit the Design Logical Effirt (English) provides a simple and universally valid method used to estimate the factors such as topology. capacitance caused by the delay. High-speed CMOS circuits the Design Logical Effirt method (English version) practical. suitable for integrated circuit designers and professional students and teachers. Contents: 1 The Method of Logical Effort1.1 Intro...
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