Digital Logic Design Using Verilog: Coding and Rtl Synthesis - Couverture souple

Taraate, Vaibbhav

Couverture souple

ISBN 10 : 8132238389 ISBN 13 : 9788132238386

Editeur : Springer, India, Private Ltd, 2018

Synopsis

This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design.

A propos du livre

À propos de l?auteur

Vaibbhav Taraate is Entrepreneur and Mentor at "Semiconductor Training @ Rs.1". He holds a BE (Electronics) degree from Shivaji University, Kohlapur in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his MTech (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 Years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.

Détails de l'édition

• Éditeur: Springer, India, Private Ltd
• Date d'édition: 2018
• Langue: anglais
• ISBN 10: 8132238389
• ISBN 13: 9788132238386
• Reliure: Broché
• Nombre de pages: 439
• Coordonnées du fabricant: ProductSafety@springernature.com; ProductSafety@springernature.com; ; Poststr. 9; Darmstadt; 64293; Allemagne