Articles liés à Analog-Baseband Architectures and Circuits for Multistandard...

Analog-Baseband Architectures and Circuits for Multistandard and Low-Voltage Wireless Transceivers - Couverture souple

Livre 6 sur 124: Analog Circuits and Signal Processing

Mak, Pui-In; U Seng Pan, Ben; Martins, Rui Paulo

 
9789048176403: Analog-Baseband Architectures and Circuits for Multistandard and Low-Voltage Wireless Transceivers

Synopsis

This book presents architectural and circuit techniques for wireless transceivers to achieve multistandard and low-voltage compliance. It provides an up-to-date survey and detailed study of the state-of-the-art transceivers for modern single- and multi-purpose wireless communication systems. The book includes comprehensive analysis and design of multimode reconfigurable receivers and transmitters for an efficient multistandard compliance.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

À propos de l'auteur

received the Ph.D. degree from University of Macau (UM), Macao, China, in 2006. He is currently Professor at UM Faculty of Science and Technology – ECE Department, Director at the State Key Laboratory of Analog and Mixed-Signal VLSI and Deputy Director (Research) at the Institute of Microelectronics. His research interests are on analog and radio-frequency (RF) circuits and systems for wireless and multidisciplinary innovations. His involvements with IEEE are: Editorial Board Member of IEEE Press (’14-’16); Member of Board-of-Governors of IEEE Circuits and Systems Society (’09-’11); Senior Editor of IEEE Journal on Emerging and Selected Topics in Circuits and Systems (’14-’15); Associate Editor of IEEE Journal of Solid-State Circuits (’18-), IEEE Solid-State Circuits Letters (’17-), IEEE Transactions on Circuits and Systems I (’10-’11, ’14-’15) and II (’10-’13). He is/was the TPC Vice Co-Chair of ASP-DAC (’16), TPC Member of A-SSCC (’13-’16,’19), ESSCIRC (’16-’17) and ISSC

À propos de la quatrième de couverture

With the past few decade efforts on lithography and integrated-circuit (IC) technologies, very low-cost microsystems have been successfully developed for many different applications. The trend in wireless communications is toward creating a networkubiquitous era in the years to come. Many unprecedented opportunities and challenges, such as Design for multi-standardability and low-voltage (LV) compliance, are rapidly becoming the mainstream directions in wireless-IC research and development, given that the former can offer the best connectivity among different networks, while the latter can facilitate the technology migration into the sub-1-V nanoscale regimes for further cost and power reduction.

Analog-Baseband Architecturees and Circuits presents architectural and circuit techniques for wireless transceivers to achieve multistandard and low-voltage compliance. The first part of the book reviews the physical layer specifications of modern wireless communication standards, presents the fundamental tradeoffs involved in transceiver architecture selection, and provides case studies of the state-of-the-art multistandard transceivers, where the key techniques reinforced are highlighted and discussed. A statistical summary (with 100+ references cited) of most used transmitter and receiver architectures for modern communication standards is provided. All the references are citied from the leading forums, i.e., ISSCC, CICC, VLSI and ESSCIRC, from 1997 to 2005.

The second part focuses on the architectural design of multistandard transceivers. A coarse-RF fine-IF (two-step) channelselection technique is disclosed. It, through the reconfiguration of receiver and transmitter analog basebands, enables not only a relaxation of the RF frequency synthesizer s and local oscillator s design specifications, but also an efficient multistandard compliance by synthesizing the low-IF and zero-IF in the receiver; and the direct-up and two-step-up in the transmitter. The principle is demonstrated in few design examples. One of them is a system-in-a-package (SiP) receiver analog  baseband for IEEE 802.11a/b/g WLAN. It not only has the two-step channel selection embedded, but also features a flexible-IF topology, a unique 3D-stack floorplan, and a particular design methodology for high testability and routability.

The third part deals with the circuit design. In addition to the methodical description of many LV circuit techniques, 3 tailormade LV-robust functional blocks are presented. They include: 1) a double-quadrature-downconversion filter (DQDF) it realizes concurrently clock-rate-defined IF reception, I/Q demodulation, IF channel selection and baseband filtering. 2) A switched-current-resistor (SCR) programmable-gain amplifier (PGA) it offers a transient-free constant-bandwidth gain adjustment. 3) An inside-OpAmp dc-offset canceler it saves the silicon area required for realizing a large time constant on chip while maximizing its highpass-pole switchability for fast dc-offset transient.

The last part presents experimental results of the 3 tailor-made building blocks and a fully-integrated analog-baseband IC fabricated in a standard-VTH CMOS process. Previously untold on-/off-chip co-setup for both full-chip and building blocks measurements are described. Not only the building blocks have successfully extended the state-of-the-art boundary in terms of signal bandwidth and supply voltage, the analog-baseband IC has been so far the lowest-voltage-reported solution for IEEE 802.11a/b/g WLAN receivers.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.