Planar Double-Gate Transistor: From technology to circuit - Couverture souple

Couverture souple

ISBN 10 : 9048181089 ISBN 13 : 9789048181087

Editeur : Springer, 2010

Synopsis

Until the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore’s law and each dif?culty has found a solution.

Détails de l'édition

• Éditeur: Springer
• Date d'édition: 2010
• Langue: anglais
• ISBN 10: 9048181089
• ISBN 13: 9789048181087
• Reliure: Broché
• Numéro d'édition: 1
• Nombre de pages: 220
• Éditeur: Amara Amara, Rozeau Olivier
• Coordonnées du fabricant: non disponible
• Personne responsable: CMN Printpool Inh. Mathis Neumann; https://www.also.com/ec/cms5/en_6000/6000/index.jsp; ; Friedrich-Karl-Str. 9; Hamburg; Allemagne