VLSI Design - Couverture souple

Bagad, V S

 
9789350388921: VLSI Design
Couverture souple
ISBN 10 : 9350388928 ISBN 13 : 9789350388921
Editeur : Technical Publications, 2013

Synopsis

UNIT - I CMOS Technology (Chapter - 1) A brief history-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non-ideal I-V effects, DC transfer characteristics - CMOS technologies, Layout design rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues. UNIT - II Circuit Characterization and Simulation (Chapter - 2) Delay estimation, Logical effort and transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling - SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation. UNIT - III Combinational and Sequential Circuit Design (Chapter - 3) Circuit families - Low power logic design - Comparison of circuit families - Sequencing static circuits, Circuit design of latches and flip flops, Static sequencing element methodology - Sequencing dynamic circuits - Synchronizers. UNIT - IV CMOS Testing (Chapter - 4) Need for testing - Testers, Taxt fixtures and test programs - Logic verification - Silicon debug principles - Manufacturing test - Design for testability - Boundary scan. UNIT - V Specification using Verilog HDL (Chapter - 5) Basic concepts - Identifiers - Gate primitives, Gate delays, Operators, Timing controls, Procedural assignments conditional statements, Data flow and RTL, Structural gate level switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, structural gate level description of decoder, Equality detector, Compatator, Priority encoder, Half adder, Full adder, Ripple carry adder, D latch and D flip-flop.

Les informations fournies dans la section « Synopsis » peuvent faire référence à une autre édition de ce titre.

Présentation de l'éditeur

UNIT - I CMOS Technology (Chapter - 1) A brief history-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non-ideal I-V effects, DC transfer characteristics - CMOS technologies, Layout design rules, CMOS process enhancements, Technology related CAD issues, Manufacturing issues. UNIT - II Circuit Characterization and Simulation (Chapter - 2) Delay estimation, Logical effort and transistor sizing, Power dissipation, Interconnect, Design margin, Reliability, Scaling - SPICE tutorial, Device models, Device characterization, Circuit characterization, Interconnect simulation. UNIT - III Combinational and Sequential Circuit Design (Chapter - 3) Circuit families - Low power logic design - Comparison of circuit families - Sequencing static circuits, Circuit design of latches and flip flops, Static sequencing element methodology - Sequencing dynamic circuits - Synchronizers. UNIT - IV CMOS Testing (Chapter - 4) Need for testing - Testers, Taxt fixtures and test programs - Logic verification - Silicon debug principles - Manufacturing test - Design for testability - Boundary scan. UNIT - V Specification using Verilog HDL (Chapter - 5) Basic concepts - Identifiers - Gate primitives, Gate delays, Operators, Timing controls, Procedural assignments conditional statements, Data flow and RTL, Structural gate level switch level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, structural gate level description of decoder, Equality detector, Compatator, Priority encoder, Half adder, Full adder, Ripple carry adder, D latch and D flip-flop.

Les informations fournies dans la section « A propos du livre » peuvent faire référence à une autre édition de ce titre.

Éditeur
Technical Publications
Date d'édition
2013
Langue
anglais
ISBN 10 
9350388928
ISBN 13 
9789350388921
Reliure
Broché
Numéro d'édition
3
Nombre de pages
460
Coordonnées du fabricant
non disponible
Personne responsable
non disponible