Logic Synthesis and Soc Prototyping: Rtl Design Using Vhdl - Couverture souple

Taraate, Vaibbhav

Couverture souple

ISBN 10 : 9811513163 ISBN 13 : 9789811513169

Editeur : Springer Verlag, Singapore, 2021

Synopsis

Emphasises SOC architecture and micro-architecture design with case studies

Consists of the practical scenarios and issues and helpful to graduate students and professionals

Covers SOC Design, implementation using VHDL, Synthesis and timing analysis

Covers key case studies in the generic form for processor, buses, interfaces, memory controllers, DSP and Video controllers

A propos du livre

À propos de l?auteur

Vaibbhav Taraate is Entrepreneur and Mentor at "1 Rupee S T". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 15 years ofexperience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Détails de l'édition

• Éditeur: Springer Verlag, Singapore
• Date d'édition: 2021
• Langue: anglais
• ISBN 10: 9811513163
• ISBN 13: 9789811513169
• Reliure: Broché
• Nombre de pages: 270
• Coordonnées du fabricant: ProductSafety@springernature.com; ProductSafety@springernature.com; ; Poststr. 9; Darmstadt; 64293; Allemagne