Computer Architecture Techniques for Power-Efficiency

Margaret Martonosi

ISBN 10: 3031005937 / ISBN 13: 9783031005930

Edité par Springer International Publishing Jun 2008, 2008

A propos de cet article

This item is printed on demand - it takes 3-4 days longer - Neuware -In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. Table of Contents: Introduction / Modeling, Simulation, and Measurement / Using Voltage and Frequency Adjustments to Manage Dynamic Power / Optimizing Capacitance and Switching Activity to Reduce Dynamic Power / Managing Static (Leakage) Power / Conclusions 220 pp. Englisch.

N° de réf. du vendeur 9783031005930

Détails bibliographiques

• Titre: Computer Architecture Techniques for Power-Efficiency
• Éditeur: Springer International Publishing Jun 2008
• Date de parution: 2008
• Langue: anglais
• ISBN à 10 chiffres: 3031005937
• ISBN à 13 chiffres: 9783031005930
• Reliure: Taschenbuch
• État de l'article: Neu
• Dimensions: 235 L x 191 H x 13 P (en millimètres) 235 millimètres de largeur par 191 millimètres de hauteur par 13 millimètres de profondeur
• Poids: 420 grammes

A propos de ce titre

Synopsis

In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and aslowdown in frequency increase. This book aims to document some of the most important architectural techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in processors and memory hierarchies. A significant number of techniques have been proposed for a wide range of situations and this book synthesizes those techniques by focusing on their common characteristics. Table of Contents: Introduction / Modeling, Simulation, and Measurement / Using Voltage and Frequency Adjustments to Manage Dynamic Power / Optimizing Capacitance and Switching Activity to Reduce Dynamic Power / Managing Static (Leakage) Power / Conclusions

À propos de l'auteur

Stefanos Kaxiras is a full professor at Uppsala University, Sweden. He holds a Ph.D. degree in Computer Science from the University of Wisconsin. In 1998, he joined the Computing Sciences Center at Bell Labs (Lucent) and later Agere Systems. In 2003 he joined the faculty of the ECE Department of the University of Patras, Greece and in 2010 became a full professor at Uppsala University, Sweden. Kaxiras' research interests are in the areas of memory systems, and multiprocessor/multicore systems, with a focus on power efficiency. He has co-authored more than 100 research papers and 13 US patents, participated in five major European research projects, and currently receives funding from Swedenâ (TM)s business incubator and innovation agency VINNOVA. Kaxiras is a Distinguished ACM Scientist and IEEE member. Margaret Martonosi is the Hugh Trumbull Adams '35 Professor of Computer Science at Princeton University, where she has been on the faculty since 1994. She also holds an affiliated faculty appointment in Princeton EE. Martonosi's research interests are in computer architecture and mobile computing, with particular focus on power-efficient systems. Her work has included the development of the Wattch power modeling tool and the Princeton ZebraNet mobile sensor network project for the design and real-world deployment of zebra tracking collars in Kenya. Her current research focuses on hardware-software interface approaches to manage heterogeneous parallelism and power-performance tradeoffs in systems ranging from smartphones to chip multiprocessors to large-scale data centers. Martonosi is a Fellow of both IEEE and ACM. She was the 2013 recipient of the Anita Borg Institute Technical Leadership Award. She has also received the 2013 NCWIT Undergraduate Research Mentoring Award and the 2010 Princeton University Graduate Mentoring Award. In addition to many archival publications, Martonosi is an inventor on six granted US patents, and has co-authored a technical reference book on power-aware computer architecture. She serves on the Board of Directors of the Computing Research Association (CRA). Martonosi completed her Ph.D. at Stanford University, and also holds a Master's degree from Stanford and a bachelor's degree from Cornell University, all in Electrical Engineering.